Scheduling Techniques of AI Models on Modern Heterogeneous Edge GPU -- A Critical Review

Ashiyana Abdul Majeed; Mahmoud Meribout; Safa Mohammed Sali

REVIEW 3 major objections 5 minor 43 references

Scheduling Techniques of AI Models on Modern Heterogeneous Edge GPU -- A Critical Review

T0 review · 3 major / 5 minor · reviewed 2026-08-07 · deepseek-v4-flash

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Pith's one-line read This review maps ten DNN schedulers for NVIDIA Jetson devices and argues the field has converged on a single DLA-to-GPU transition point, leaving the PVA and VIC accelerators unused.

desk verdict A useful survey of recent Jetson schedulers with a real gap analysis, but the comparative table contradicts its own energy claim and needs recomputation. read the letter →

arxiv 2506.01377 v2 pith:CMM6YIKM submitted 2025-06-02 cs.DC cs.AR

Ashiyana Abdul Majeed , Mahmoud Meribout , Safa Mohammed Sali This is my paper

classification cs.DCcs.AR

keywords DNNschedulingNVIDIAJetsondeeplearningaccelerator(DLA)heterogeneousedgecomputingmemorycontentiontransitioncostGPU-DLApartitioningAI

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This review paper sets out to map the state of the art in scheduling deep neural networks on recent NVIDIA Jetson edge devices, which combine a CPU, GPU, deep learning accelerator (DLA), programmable vision accelerator (PVA), and video image compositor (VIC). It compares ten schedulers by their methodology, performance goals, and measured results, and argues that the field has converged on a single design pattern: partition the network at one transition point and run early layers on the DLA and later layers on the GPU. The review's practical contribution is a comparative map showing which scheduler fits which workload: HaX-CoNN for multiple concurrent DNNs, CP-CNN and Jedi for real-time single-model frame processing, and AxoNN or Map-and-Conquer when energy is the priority. It also identifies an open gap: no published scheduler makes use of the PVA or VIC, in part because NVIDIA's own frameworks restrict DNN layers to the DLA or GPU.

What carries the argument

The object that carries the argument is the layer-to-device mapping problem on a heterogeneous system-on-chip: each layer $N_n$ of a DNN is assigned to a processing element $s(N_n)$ (CPU, GPU, or DLA), and the cost of a schedule is the sum of per-layer latency or energy plus a transition cost $\tau$ whenever consecutive layers run on different devices. The review uses this formalism to classify schedulers by how they choose the transition point: heuristic search (Jedi, CP-CNN), linear programming (LP), satisfiability-modulo-theories solvers (AxoNN, HaX-CoNN), or evolutionary algorithms (GA, Map-and-Conquer, MaGNAS). It then uses the comparative tables to explain why most schedulers converge on one DLA-to-GPU transition: frequent switching adds data-transfer overhead and solver time.

What would settle it

Run one of the surveyed schedulers, for example Jedi or HaX-CoNN, on a Jetson AGX Orin with the same DNNs used in the original papers, and check whether the optimal transition layer and measured speedups match the Xavier results; a mismatch would refute the claim that the devices are similar enough for results to transfer. In addition, a single published scheduler that assigns DNN layers to the PVA or VIC, or a TensorRT release that allows such assignments, would directly contradict the paper's stated gap.

Watch

Extended reading notes

Core claim

The paper's central claim is that, for NVIDIA Jetson AGX devices that include a DLA, the dominant and most effective scheduling strategy is to split each DNN once, running the early feature-extraction layers on the DLA and the later detection or classification layers on the GPU, with a single transition between the two. It further argues that among the reviewed schedulers, HaX-CoNN is the most versatile for multi-DNN workloads because its satisfiability-based search handles concurrent and changing DNN sets, while Map-and-Conquer is the most adaptable in model architecture because it parallelizes individual inference stages horizontally and supports transformer models. The review also claims that the PVA and VIC accelerators remain entirely unused by schedulers, and that NVIDIA frameworks such as TensorRT and DeepStream prevent DNN layers from being assigned to them, leaving a concrete opportunity for future work.

Load-bearing premise

The comparisons and rankings assume that throughput, latency, and energy numbers taken from different papers, measured on different setups and hardware, are comparable enough to rank, and that results measured on the Xavier carry over to the Orin because the two devices are 'similar architecturally.'

Editorial extensions

If this is right

If the review's map is right, a practitioner choosing a scheduler for Jetson AGX can select by workload type: HaX-CoNN for concurrent multi-DNN streams, CP-CNN or Jedi for real-time frames of one detector, and AxoNN or Map-and-Conquer for energy-constrained inference.
The single-transition DLA-to-GPU pattern implies that future schedulers can be simplified: most gains come from one carefully placed cut point rather than from frequent layer switching.
Because no scheduler uses PVA or VIC, adding those accelerators to the partition space could yield further speedups or energy savings without changing the core scheduling methods.
The claim that Orin behaves like Xavier implies that existing schedulers can be ported to Orin without re-profiling, which would save substantial engineering effort if true.
TensorRT's restriction of DNN layers to DLA or GPU means that until NVIDIA's toolchain changes, PVA and VIC use will be limited to pre- and post-processing, bounding what any scheduler can do.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

Beyond the paper: the approximate energy values for Jedi and GA in Table I suggest the quantitative rankings are weaker than the qualitative ordering, so a controlled re-benchmark on identical hardware would be needed to confirm the throughput and energy comparisons.
Beyond the paper: if the Xavier-to-Orin architectural-similarity premise fails, the field's reliance on Xavier measurements may have to be revisited; one concrete test is to run Jedi or HaX-CoNN on Orin and compare the chosen transition point.
Beyond the paper: the review's gap analysis suggests a research program of extending existing schedulers to a three- or four-accelerator partition space (DLA plus GPU plus PVA plus VIC) once NVIDIA's layer-assignment constraints are relaxed or worked around.
Beyond the paper: as the field moves toward LLM inference on edge devices, the single-transition DLA-GPU pattern may need re-examination for transformer layers, which Map-and-Conquer already handles but most other schedulers do not.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Two things you should know. This is a genuinely useful survey of ten DNN schedulers for NVIDIA Jetson devices—the first review I've seen that covers post-2022 work like HaX-CoNN, Map-and-Conquer, and MaGNAS. The classification into heuristic vs. optimization, static vs. dynamic, and vertical vs. horizontal is sensible; the hardware background is standard but accurate; and the gap analysis (PVA and VIC unused, TensorRT restricting DNN layers to DLA or GPU) is the kind of thing practitioners will actually act on.

The soft spot is load-bearing, not cosmetic. Section IV claims CP-CNN reduces energy per image by 62–84%, but Table I lists GPU-only at 329–460 mJ and CP-CNN at 306 mJ—that's a 7–33% reduction. One of those statements is wrong or uses a different baseline. Since the Section V ranking of Jedi, CP-CNN, and GA follows directly from that table, the contradiction undermines the paper's central comparison. The table's own footnote makes it worse: two rows are approximate (energy divided by image count), and the GPU-only range is drawn from two different papers. The rows are not commensurable. This is fixable by rebuilding one properly sourced table, but as written it cannot support the rankings.

The other issues are more minor but real. The assumption in Section III that Xavier-era results extend to Orin because the devices are "similar architecturally" is asserted, not tested; Volta vs. Ampere and two different DLA generations are not close enough to skip the measurement. The novelty claim rests on comparing with only two surveys, which makes it plausible but undemonstrated.

Bottom line: the survey fills a real gap and a practitioner will get value from it. But the internal contradiction in Table I needs to be resolved before the comparative conclusions can be relied on. I'd send it to peer review with a request for revision: recompute the table, reconcile the CP-CNN claim, soften the Orin extrapolation, and broaden the related-work comparison. It's not a desk reject.

Referee Report

3 major / 5 minor

Summary. This paper is a literature review of DNN scheduling techniques for NVIDIA Jetson edge devices, covering ten schedulers (Jedi, CP-CNN, Herald, H2H, LP, AxoNN, GA, HaX-CoNN, Map-and-Conquer, MaGNAS). It organizes the field according to heuristic versus optimization-based methods, static versus dynamic behavior, and inter- versus intra-accelerator parallelism, and it compares reported performance on the Jetson AGX Xavier. The review identifies the absence of schedulers that use the PVA and VIC accelerators and notes that TensorRT restricts DNN layer assignment to DLA or GPU. Its main conclusions are that the field tends toward a single DLA-to-GPU transition point, that HaX-CoNN is particularly versatile for multi-DNN workloads, that Map-and-Conquer is flexible in model architecture, and that CP-CNN and Jedi are suitable for real-time single-DNN workloads.

Significance. If the reported comparisons are reliable, the paper offers a useful structured map of a small but fast-moving literature and identifies a concrete gap: no scheduler exploits the PVA or VIC accelerators, and NVIDIA's frameworks currently block such use for DNN layers. The taxonomy is sensible, the gap analysis is actionable, and the paper usefully distinguishes static from dynamic schedulers and horizontal from vertical partitioning. The review contains no original measurements, so its value depends entirely on faithful and internally consistent reporting of the surveyed papers. That consistency currently fails at a load-bearing point: the energy comparison in Table I contradicts the text's quantitative claim, and the table mixes non-commensurable rows. The review also extends Xavier-era results to the Orin without support, despite its own description of architectural differences. These problems are repairable, but they undermine the central comparative claims as written.

major comments (3)

[Section IV and Table I] The text states that 'CP-CNN reduces the energy consumed per image by 62% to 84%,' but Table I lists GPU-only energy at 329-460 mJ per image and CP-CNN at 306 mJ, which corresponds to a reduction of only about 7% to 33%. Either the 62-84% figure is against a different baseline than the table's GPU-only column, or the table is incorrect. Because this comparison is the basis for the later claim that CP-CNN is ideal for real-time single-DNN workloads, the discrepancy must be resolved by recomputing the table with a single clearly defined baseline or by explicitly reporting the original baselines from [8].
[Section III] The claim that 'since both Xavier and Orin device are similar architecturally, the schedulers are expected to function similarly' is load-bearing for the paper's stated scope of 'more recent NVIDIA edge devices,' but it is unsupported. Section II documents substantial differences between the two platforms: Volta versus Ampere GPUs, different DLA versions, different CPU cores, an added L2 cache in the Orin PVA, different VIC frequency limits, and different memory systems. No Orin measurements or quantitative invariance argument are provided. This extrapolation should be either backed with data or explicitly reframed as an untested hypothesis.
[Table I] The footnote that the energy values for Jedi and GA were 'calculated approximately by dividing the energy by the number of images used for inference' makes the rows non-commensurable with the GPU-only and CP-CNN rows, which are presented as per-image measurements. Adding a GPU-only range taken from two different papers further mixes baselines. As constructed, Table I cannot support the cross-scheduler ranking in Section IV or the conclusion that Jedi and CP-CNN are leading choices for real-time single-DNN workloads. The authors should replace the table with a consistent set of measured figures or explicitly state that the rows are not directly comparable and remove the resulting rankings.

minor comments (5)

[Abstract] The phrase 'optimal execution of optimal execution of deep neural network' contains a duplicated phrase and should be corrected to 'optimal execution of deep neural networks'.
[Throughout] The accelerator is sometimes written as 'PV A' with a space (e.g., in the abstract and Section II.B); the standard abbreviation 'PVA' should be used consistently.
[Section IV] The sentence 'the increasing throughput across the different models does not cause an increase in power consumption, which is usually not the case' is unclear: it should specify whether the usual expectation is that power grows with throughput, and it should distinguish between total power and energy per inference.
[Sections II.D.5 and IV] The taxonomy defines horizontal scheduling as width-wise partitioning of a model, but Section IV attributes Jedi's improvement to 'horizontal parallelization occurring within the accelerators,' which seems to refer to intra-accelerator multistreaming. These uses of 'horizontal' should be reconciled to avoid confusing the reader.
[Table I] The blank cells for CP-CNN's latency and throughput and for Jedi's latency are unexplained; adding 'not reported' or a dash with a note would make the table easier to interpret.

Circularity Check

0 steps flagged · score 0.0 of 10

No internal circularity: the review synthesizes externally measured scheduler results and performs no derivation that reduces to its own inputs.

full rationale

This is a critical review of ten external schedulers for NVIDIA Jetson devices. The review authors are not authors of any surveyed scheduler, and the comparative tables and figures are drawn from the cited primary papers (e.g., [7], [8], [33]). The paper performs no fitting, no prediction from its own model, and no derivation whose conclusion is equivalent to its premises. The central claims—that Jedi and CP-CNN are leading for single-DNN real-time workloads, that HaX-CoNN is versatile for multi-DNN, and that Map-and-Conquer supports transformer-like architectures—are summaries of externally reported measurements and methodologies, not results manufactured by the review itself. The self-citations among the surveyed papers (e.g., HaX-CoNN and AxoNN share authors [7], [32]) are not load-bearing for this review's own argument, since the review merely reports their stated numbers and does not invoke any uniqueness theorem or ansatz from those papers to justify its own categories. The reviewer's noted issues are correctness and comparability concerns, not circularity: the Table I footnote that energy values for Jedi and GA were 'calculated approximately by dividing the energy by the number of images used for inference' weakens cross-scheduler comparability, and the statement that 'Since both Xavier and Orin device are similar architecturally, the schedulers are expected to function similarly' is an untested extrapolation, but neither reduces the review's conclusions to its inputs by construction. The apparent contradiction between the claimed '62% to 84%' energy reduction for CP-CNN and the Table I values (329–460 mJ GPU-only vs 306 mJ CP-CNN) is an internal consistency or sourcing defect in the reviewed data, not a circularity in the review's reasoning. The paper is self-contained as a literature survey; its value depends on the reliability of its sources and the fairness of its comparisons, which are external-evidence limitations rather than circular derivation. Therefore the circularity score is 0.

Assumptions & free parameters 0 free parameters · 3 assumptions · 0 invented entities

This paper's claims rest on borrowed premises rather than on any derivation or fitting, which is typical for a survey. The comparative rankings assume that benchmark numbers taken from different papers, measured on different setups, are comparable (Section IV, Tables I and II). The future-work claims assume that Xavier and Orin are similar enough for results to transfer (Section III). The gap analysis assumes the surveyed set is complete, including the negative claim that no scheduler uses the PVA or VIC (Section II.B). There are no free parameters and no invented entities.

assumptions (3)

domain assumption Benchmark numbers reported in the surveyed papers are accurate and sufficiently comparable across papers to support the rankings in Tables I and II.
Section IV ranks schedulers by throughput, latency, and energy readings taken from different publications with different models and measurement conditions; Table I even notes that two energy values were derived by approximation.
domain assumption Xavier and Orin are architecturally similar enough that schedulers developed and tuned on Xavier will function similarly on Orin.
Section III states 'Since both Xavier and Orin device are similar architecturally, the schedulers are expected to function similarly,' extending all surveyed Xavier-based results to the Orin without measurements.
domain assumption The surveyed set of ten schedulers is comprehensive, including the negative claim that no scheduler uses the PVA or VIC accelerators.
Section II.B asserts 'no paper has made use of the PVA and VIC module when scheduling tasks' based on the authors' knowledge rather than a documented systematic search, and this negative claim drives the paper's main future-work direction.

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Cite this review

Pith. "Pith review of Scheduling Techniques of AI Models on Modern Heterogeneous Edge GPU -- A Critical Review." pith.science (2026). https://pith.science/paper/CMM6YIKM

@misc{pith2026250601377,
  author       = {Pith},
  title        = {Pith review of: Scheduling Techniques of AI Models on Modern Heterogeneous Edge GPU -- A Critical Review},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/CMM6YIKM}},
  note         = {Machine review of arXiv:2506.01377}
}

read the original abstract

In recent years, the development of specialized edge computing devices has significantly increased, driven by the growing demand for AI models. These devices, such as the NVIDIA Jetson series, must efficiently handle increased data processing and storage requirements. However, despite these advancements, there remains a lack of frameworks that automate the optimal execution of optimal execution of deep neural network (DNN). Therefore, efforts have been made to create schedulers that can manage complex data processing needs while ensuring the efficient utilization of all available accelerators within these devices, including the CPU, GPU, deep learning accelerator (DLA), programmable vision accelerator (PVA), and video image compositor (VIC). Such schedulers would maximize the performance of edge computing systems, crucial in resource-constrained environments. This paper aims to comprehensively review the various DNN schedulers implemented on NVIDIA Jetson devices. It examines their methodologies, performance, and effectiveness in addressing the demands of modern AI workloads. By analyzing these schedulers, this review highlights the current state of the research in the field. It identifies future research and development areas, further enhancing edge computing devices' capabilities.

Figures

Figures reproduced from arXiv: 2506.01377 by the authors.

**Figure 2.** Block diagram of the DLA 4) Programming Vision Accelerator (PVA): In both devices, the PVA consists of a Cortex-R5 chip, 2 direct memory access (DMA) engines, and 2 very long instruction word (VLIW) vector processing unit (VPU). The Orin device includes an L2 memory cache of 1MB in its PVA module [13]. It is adequate to handle relatively light, post-processing tasks like feature detection, stereo disparity, visual… view at source ↗

**Figure 4.** The Jedi scheduler does not tackle memory contention. [PITH_FULL_IMAGE:figures/full_fig_p004_4.png] view at source ↗

Figures from the paper (10 more)

**Figure 3.** Figure 3: Pipeline of the Jedi scheduler [33] [PITH_FULL_IMAGE:figures/full_fig_p005_3.png]

**Figure 5.** Figure 5: Timing diagram of the model (a) under GPU [PITH_FULL_IMAGE:figures/full_fig_p005_5.png]

**Figure 6.** Figure 6: Timing diagram of the DNNs and RNNs present in [PITH_FULL_IMAGE:figures/full_fig_p006_6.png]

**Figure 7.** Figure 7: Feasibility ratio versus utilization ratio with the LP [PITH_FULL_IMAGE:figures/full_fig_p006_7.png]

**Figure 10.** Figure 10: Comparison between the actual and predicted (by [PITH_FULL_IMAGE:figures/full_fig_p007_10.png]

**Figure 8.** Figure 8: Performance of convolution and pooling layers of [PITH_FULL_IMAGE:figures/full_fig_p007_8.png]

**Figure 9.** Figure 9: Performance of convolution and pooling layers of [PITH_FULL_IMAGE:figures/full_fig_p007_9.png]

**Figure 11.** Figure 11: Timing diagram of HaX-CoNN scheduling (case 3) [PITH_FULL_IMAGE:figures/full_fig_p007_11.png]

**Figure 12.** Figure 12: Dynamic execution case where the system changes [PITH_FULL_IMAGE:figures/full_fig_p008_12.png]

**Figure 13.** Figure 13: Throughput and energy consumption of different DNN models when executed on Xavier using the schedulers. Y [PITH_FULL_IMAGE:figures/full_fig_p009_13.png]

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