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How to keep pushing ML accelerator performance? Know your rooflines!

T0 review · 0 major / 5 minor · reviewed 2026-08-07 · deepseek-v4-flash

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Pith's one-line read An enhanced two-line roofline model, one for throughput and one for energy efficiency, can unify how ML accelerator designers reason about compute, memory, and data movement, and guide which optimization to pursue.

desk verdict A competent, well-organized survey that repackages the throughput and energy rooflines into a two-line framework for ML accelerators; useful for designers, but not a new research result. read the letter →

arxiv 2505.16346 v2 pith:D72YGMIR submitted 2025-05-22 cs.AR

Marian Verhelst , Luca Benini , Naveen Verma This is my paper
classification cs.AR
keywords MLacceleratorsrooflinemodelenergyefficiencyarithmeticintensitydatareusequantizationsparsityin-memorycomputing
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper claims that a pair of rooflines, one for throughput and one for energy efficiency, gives a unifying picture of what limits ML accelerator performance. The throughput roofline is extended to multiple memory levels, each with its own arithmetic intensity, while the energy roofline is a curved bound separating regimes where memory energy or compute energy dominates. Under this view, every major accelerator technique, including parallelism, data reuse, quantization, sparsity, and near/in-memory compute, shows up either as raising a roofline, shifting workloads to higher arithmetic intensity, or improving utilization toward the roofline. The practical payoff is that a designer can look at a workload's position on the two rooflines and decide whether to invest in more compute, more memory bandwidth or energy efficiency, or better mapping and reuse.

What carries the argument

The load-bearing object is the per-memory-level arithmetic intensity $AI_{L_i}=N_{op}/N_{L_i}$, the number of operations per byte fetched from memory level $L_i$. It carries the argument because both rooflines are functions of this quantity: the throughput roofline of Eq. (4) takes a minimum over the per-level bandwidth products and the compute peak, while the energy roofline of Eq. (5) sums each level's energy per access divided by the per-level intensity. Data reuse, quantization, sparsity, and memory-proximity techniques all enter the model as changes in these intensities or in the roofline parameters, which is what makes the framework unifying.

What would settle it

A concrete test: on a real accelerator, run a sparse tensor kernel and measure its per-level memory traffic, peak bandwidths, and peak MAC rate, then compute the predicted operating points from Eqs. (4) and (5). If the measured throughput and energy efficiency lie far below both rooflines and the gap cannot be explained by the utilization factors described in Section II-B, the claim that the two rooflines bound and explain accelerator efficiency for that workload is refuted. A softer check is to take two architectures with identical rooflines but different dataflow flexibility and show that workload-level efficiency differs in a way the rooflines cannot express.

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Extended reading notes

Core claim

The paper's central claim is that attainable throughput is $P_{TP}=f_{\mathrm{clk}}\min(AI_{L_n}B_{L_n},\dots,AI_{L_1}B_{L_1},A_{op})$ and attainable energy efficiency is $P_E=1/(E_{op}+\sum_i E_{L_i}/AI_{L_i})$, where $AI_{L_i}=N_{op}/N_{L_i}$ is the arithmetic intensity toward memory level $L_i$. Plotted together, these two expressions are claimed to explain where each execution regime falls and what action improves it. A distinctive consequence is that the throughput roofline has a sharp knee while the energy roofline is curved, and the two knees can sit at different arithmetic intensities, so an accelerator can be compute-bound for throughput and memory-bound for energy at the same operating point. The paper then reads the major efficiency techniques through this lens, treating sparsity as an intensity-lowering, utilization-changing effect and in-memory computing as a way to raise the compute roofline while eliminating the first-level memory diagonal, at the cost of new storage-compute coupling and utilization losses.

Load-bearing premise

The load-bearing premise is that a workload is well summarized by its arithmetic intensity at each memory level and that compute and memory latency overlap perfectly, so the minimum in the throughput equation captures latency; sparse and irregular workloads violate this, and the paper itself notes that they fall below the roofline and need hardware-specific utilization factors.

Editorial extensions

If this is right

  • A designer can classify any proposed optimization as raising the compute roofline, raising a memory roofline, moving the operating point to higher arithmetic intensity, or improving utilization, and can choose the category that addresses the actual bottleneck.
  • Because the throughput and energy knees depend on different parameters, improving peak TOPS and improving TOPS/W can require different changes to the same architecture, and a system can be compute-bound for one while memory-bound for the other.
  • Sparsity, especially unstructured sparsity, can lower effective arithmetic intensity and push a workload away from the roofline even when it reduces total operations; the paper concludes that roofline position alone is not enough to judge sparse hardware, and end-to-end energy and latency must be considered.
  • Near- and in-memory computing raise the compute roofline and reduce data-movement energy, but they couple storage and compute in ways that cause spatial and temporal utilization losses, so the full benefit depends on adding a second memory level and carefully mapping workloads.
  • Larger parallel compute arrays raise the roofline but shift the knee to higher arithmetic intensity, making the system more memory-bound unless data reuse keeps the workload's intensity high.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • A natural extension the paper does not formalize is a utilization-aware design rule: choose compute parallelism and memory bandwidth so that both knees sit near the arithmetic intensity of the target workload mix; the paper's area-allocation discussion points that way but stops short of a closed-form rule.
  • The framework suggests a reporting standard for published accelerators: give the throughput and energy rooflines together with the achieved utilization at the workload point, since identical rooflines can hide large efficiency differences; this is measurable and would make survey comparisons fairer.
  • For sparse workloads, defining a sparsity-aware arithmetic intensity that counts only non-zero operations and effective bytes with indices might restore the roofline's predictive power; the paper notes the gap but does not propose such a metric.
  • Treating the inter-chip network in multi-chip LLM systems as an additional memory level with its own bandwidth and energy per byte would extend the framework to scale-out architectures, which the paper mentions only as future outlook.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

0 major / 5 minor

Summary. This manuscript proposes an enhanced roofline modeling framework for ML accelerators, comprising a throughput roofline (Eq. 4) and an energy-efficiency roofline (Eq. 5) that account for per-level arithmetic intensities across a multi-level memory hierarchy. After deriving the two roofline equations from an additive energy model (Eq. 1) and a max-latency model (Eq. 2), the paper surveys five hardware techniques—parallelism, spatial/temporal data reuse, quantization, sparsity, and near/in-memory computing—and illustrates how each affects the roofline position and the workload operating point. It closes with trade-offs between parallelism and utilization, programmability and specialization, and an outlook on emerging technologies.

Significance. The paper's value lies in its organized synthesis and explicit two-roofline formulation. The equations are correct under the stated additive-energy and max-latency assumptions, and the paper is unusually candid about the model's limits, particularly in Section III-D and Section IV-B, where it acknowledges that sparse/irregular workloads fall below the roofline due to utilization losses and that roofline analysis alone is not sufficient for end-to-end speedup or energy decisions. No data fitting or fabricated results are involved; the illustrative parameters are clearly labeled as assumptions. These strengths make the paper a useful reference for practitioners and students, though it does not present new experimental data. The central claim is appropriately scoped as a framework for understanding rather than for prediction, so the absence of an integrated utilization factor is a limitation but not a fatal one.

minor comments (5)
  1. [Section III-F1, Eq. (6)] Equation (6) is self-referential as written: D_y appears on both sides, and the expression is dimensionally inconsistent with the surrounding prose. The text in Section III-F2 correctly states that the dynamic range in bits is the sum of input bits, weight bits, and log2(P_R). Please correct Eq. (6) to a bits-based form such as B_y = B_x + B_w + log2(P_R), or provide the equivalent linear-scale expression.
  2. [Abstract and title] The abstract and title contain the typo "rooline" instead of "roofline"; this should be corrected throughout.
  3. [Section I and Section V] The introduction states "nearly 100 × performance improvement every 24 months, maintained over the past 8 years" (which would imply an enormous cumulative factor), while the conclusion states "roughly 1000 × increase in throughput and energy efficiency." These two statements are inconsistent; please reconcile them or clarify the time scales being referenced.
  4. [Figure 3 caption] The caption's expression "AI=AIL3/16=AIL2=AIL1 ∗ 16" is ambiguous and potentially misleading. Please define the assumed relationships among the per-level arithmetic intensities explicitly, for instance by stating that each successive level differs by a factor of 16.
  5. [Section III-A] There is a typo in the first paragraph: "paralelization" should be "parallelization." Similar minor typographical errors appear elsewhere, such as "rooline" in the abstract and "the Samsung's" in Section III-A; a careful proofreading pass is recommended.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: the two-roofline equations are algebraic restatements of the paper's own latency and energy definitions, and the central framing rests on external roofline literature.

full rationale

The paper's central equations are derived directly from its own stated definitions. Equation (4) is obtained by substituting the arithmetic-intensity definition AILi = Nop/NLi into the latency expression Ltask = (1/fclk)*max(NLn/BLn,...,NL1/BL1,Nop/Aop) and writing PTP = Nop/Ltask; Equation (5) is obtained by substituting the same definition into the energy expression Etask = Nop*Eop + sum(NLi*ELi) and writing PE = Nop/Etask. These are algebraic identities given the definitions, not empirical predictions, and no parameter is fitted to data and then renamed as a prediction. The paper makes no claim to predict measured accelerator performance from first principles; it presents an organizing framework whose validity rests on the external roofline model of Williams et al. [3] and the energy roofline of Choi et al. [9]. The self-citations that are present, such as [55] for the in-memory-compute dynamic-range trade-off, are explicitly attributed as prior work ('Simplifying the more detailed analysis in [55]') and are used as surveyed examples rather than as load-bearing justification for the paper's roofline framework. The paper even concedes in Section III-D that 'Roofline analysis alone, albeit useful, is not sufficient' for sparse workloads, which is a limitation of scope rather than a circular step. No load-bearing step in the derivation chain reduces by construction to its own inputs, so the appropriate finding is no significant circularity.

Assumptions & free parameters 0 free parameters · 5 assumptions · 0 invented entities

The framework introduces no fitted parameters; the numbers in Figure 3 are illustrative and clearly labeled as assumptions from a 22nm process. The load-bearing assumptions are the standard roofline model, the additive energy model, the monotonic arithmetic-intensity hierarchy, and the perfect-overlap latency model. The IMC trade-off analysis is adopted from the authors' own [55], with provenance stated.

assumptions (5)
  • standard math The classic roofline model of Williams et al. [3] and its energy variant by Choi et al. [9] are valid starting points.
    Section II.B builds Eq. (4) and (5) directly on these prior models, which are cited. The paper adds a multi-level memory hierarchy but does not question the underlying assumptions.
  • domain assumption Energy and latency of ML accelerators are dominated by MAC operations and data movement, each with constant per-byte/per-op costs (Eq. 1).
    Section II.A. This additive energy model ignores leakage, clock gating, and non-linear scaling, but is a common first-order model in the cited literature.
  • domain assumption Arithmetic intensity varies monotonically across memory levels (AIL3 > AIL2 > AIL1) for typical ML workloads.
    Section II.B, citing [8]. This drives the multi-level roofline. It does not hold for all layers, as the paper notes for batch-1 fully connected layers.
  • domain assumption Compute and memory transfers overlap such that latency is the max of the individual times (Eq. 4).
    Section II.B. If overlap is not perfect, the sharp roof becomes a rounded curve, which the paper acknowledges in the text and attributes to [10].
  • domain assumption The dynamic-range versus parallelism trade-off in IMC is as described in [55] by Verma et al.
    Section III-F.1 says 'Simplifying the more detailed analysis in [55]', so it adopts a prior result from one of the authors as the basis for the IMC trade-off discussion.

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Cite this review

Pith. "Pith review of How to keep pushing ML accelerator performance? Know your rooflines!." pith.science (2026). https://pith.science/paper/D72YGMIR

@misc{pith2026250516346,
  author       = {Pith},
  title        = {Pith review of: How to keep pushing ML accelerator performance? Know your rooflines!},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/D72YGMIR}},
  note         = {Machine review of arXiv:2505.16346}
}
read the original abstract

The rapidly growing importance of Machine Learning (ML) applications, coupled with their ever-increasing model size and inference energy footprint, has created a strong need for specialized ML hardware architectures. Numerous ML accelerators have been explored and implemented, primarily to increase task-level throughput per unit area and reduce task-level energy consumption. This paper surveys key trends toward these objectives for more efficient ML accelerators and provides a unifying framework to understand how compute and memory technologies/architectures interact to enhance system-level efficiency and performance. To achieve this, the paper introduces an enhanced version of the roofline model and applies it to ML accelerators as an effective tool for understanding where various execution regimes fall within roofline bounds and how to maximize performance and efficiency under the rooline. Key concepts are illustrated with examples from state-of-the-art designs, with a view towards open research opportunities to further advance accelerator performance.

Figures

Figures reproduced from arXiv: 2505.16346 by the authors.

Figure 1
Figure 1. Evolution of ML model size, GPU performance and Moore’s law [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Typical architecture of an ML accelerator. Note that the amount of [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 3
Figure 3. Example roofline models for performance and energy effi [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figures from the paper (15 more)
Figure 4
Figure 4. Figure 4: Overview of various architectural and mapping techniques to maximize performance by raising the rooflines and more closely approaching the rooflines. [PITH_FULL_IMAGE:figures/full_fig_p004_4.png]
Figure 5
Figure 5. Figure 5: shows the performance of subsequent generations of Google’s TPU. As can be seen, different techniques, such as a wider the DRAM bandwidth, increased parallelism and a higher clock frequency are used to raise the roofline(1). Secondly, hardware support for quantization …
Figure 6
Figure 6. Figure 6: It is, however, important to realize that the selected paralel￾lization strategy strongly impacts the efficiency with which the parallel resources are used. This can be quantified in terms of the utilization of the processing elements. As detailed in [PITH_FULL_IMAGE:…
Figure 7
Figure 7. Figure 7: Spatial data reuse concepts B. Exploiting spatial and temporal data reuse The operands of the MAC operations in neural networks have a potential data reuse factor which can easily go up to 10,000’s. For example, the weights in a Conv layer or the operands of a large Ma…
Figure 10
Figure 10. Figure 10: RISC-V mixed-precision SIMD dot-product unit [PITH_FULL_IMAGE:figures/full_fig_p007_10.png]
Figure 11
Figure 11. Figure 11: (a) Block quantization and dot-product of block-quantized vector [PITH_FULL_IMAGE:figures/full_fig_p008_11.png]
Figure 12
Figure 12. Figure 12: Neureka mixed-precision accelerator architecture design [PITH_FULL_IMAGE:figures/full_fig_p008_12.png]
Figure 13
Figure 13. Figure 13: Nested loop for execution of a 3×3 convolutional layer in Neureka. Note that shift-and-add loop is executed sequentially bit-by-bit for the 8bit weights can be seen as one additional dimension in the nested for-loop notation discussed in section III: this is shown in …
Figure 16
Figure 16. Figure 16: Comparison of traditional, near-, and in-memory architectures [PITH_FULL_IMAGE:figures/full_fig_p010_16.png]
Figure 17
Figure 17. Figure 17: Basics of in-memory computing for MVM operations. [PITH_FULL_IMAGE:figures/full_fig_p011_17.png]
Figure 18
Figure 18. Figure 18: Fundamental dynamic-range trade-off of in-memory computing [55]. [PITH_FULL_IMAGE:figures/full_fig_p012_18.png]
Figure 19
Figure 19. Figure 19: Generalized column computation in in-memory computing. [PITH_FULL_IMAGE:figures/full_fig_p012_19.png]
Figure 21
Figure 21. Figure 21: Switched-capacitor in-memory computing for high-SNR computa [PITH_FULL_IMAGE:figures/full_fig_p013_21.png]
Figure 20
Figure 20. Figure 20: Analysis of digital in-memory computing versus standard digital [PITH_FULL_IMAGE:figures/full_fig_p013_20.png]
Figure 22
Figure 22. Figure 22: Roofline optimizations to different workload arithmetic intensities. [PITH_FULL_IMAGE:figures/full_fig_p014_22.png]

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