Typed states for the displayed outbound observations.
Source: paper_references, paper_reference_links
Paper Citation Record · LEDGER
(Security) Assertions by Large Language Models
As of 7 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 6 inbound Pith citation observations for arXiv:2306.14027.
A citation records a reference. It does not transfer a finding from one paper to another.
Coverage vector
One-hop event checks from named stored sources.
Source: scholarly_work_events, retraction_status_cache, observed 2026-08-07T06:34:17.273281+00:00
Pith citing papers itemized under the disclosed page cap.
Source: paper_references, paper_reference_links, observed 2026-08-07T13:00:51.097081Z
A source-named dated measurement, never combined with another source.
Source: arxiv_reference, observed 2026-05-15T14:35:55.918162Z
Reference resolution
0 of 0 outbound references displayed
- verified exact0
- verified fuzzy0
- unresolved0
- parse uncertain0
- malformed identifier0
- metadata mismatch0
External citation measurements
No source-named external measurement is stored.
Outbound references
No outbound reference observations are available for this paper version.
Pith citing papers
Observation e46ba1f6-cfca-43fa-acfd-bf2cd7a2aabc · inbound
BugWhisperer: Fine-Tuning LLMs for SoC Hardware Vulnerability Detection cites this paper.
BugWhisperer: Fine-Tuning LLMs for SoC Hardware Vulnerability Detection (Security) Assertions by Large Language Models
Reference 10
- Resolution
- unresolved
- no resolver link, observed 2026-08-07T13:00:51.097081Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation ce441583-6141-4dbe-9ab1-1c4486ef0478 · inbound
SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine cites this paper.
SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine (Security) Assertions by Large Language Models
Reference 1
- Resolution
- unresolved
- no resolver link, observed 2026-08-07T04:52:57.629981Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 0b26ba63-56e8-4b94-95e7-886d6f1cb97a · inbound
RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs cites this paper.
RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs (Security) Assertions by Large Language Models
Reference 19
- Resolution
- unresolved
- no resolver link, observed 2026-08-06T15:19:53.331516Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 4dc99c21-b227-4cac-a0bf-3c0296023d82 · inbound
SVAgent: AI Agent for Hardware Security Verification Assertion cites this paper.
SVAgent: AI Agent for Hardware Security Verification Assertion (Security) Assertions by Large Language Models
Reference 12
- Resolution
- unresolved
- no resolver link, observed 2026-08-06T15:22:32.913943Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation ed27f86b-2232-4d7b-9178-dfaa8a68d7b8 · inbound
FVRuleLearner: Operator-Level Reasoning Tree (Op-Tree)-Based Rules Learning for Formal Verification cites this paper.
FVRuleLearner: Operator-Level Reasoning Tree (Op-Tree)-Based Rules Learning for Formal Verification (Security) Assertions by Large Language Models
Reference 9
- Resolution
- verified exact
- arxiv_id, observed 2026-05-15T14:35:55.920120Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.
Observation 300ab7ec-f714-4f93-a16f-e6c02bcce2cc · inbound
FVRuleLearner: Operator-Level Reasoning Tree (Op-Tree)-Based Rules Learning for Formal Verification cites this paper.
FVRuleLearner: Operator-Level Reasoning Tree (Op-Tree)-Based Rules Learning for Formal Verification (Security) Assertions by Large Language Models
Reference 9
- Resolution
- unresolved
- no resolver link, observed 2026-08-02T18:43:43.026720Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.