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Counterexample Guided Synthesis of Switched Controllers for Reach-While-Stay Properties

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arxiv 1505.01180 v3 pith:EEXGPIEC submitted 2015-05-05 cs.SY cs.SY

classification cs.SY
keywords approachcontrollersswitchingsynthesiscontrolguaranteeguidedintroduce
verification ladder T0 review T1 audit T2 compute T3 formal

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We introduce a counter-example guided inductive synthesis (CEGIS) framework for synthesizing continuous-time switching controllers that guarantee reach while stay (RWS) properties of the closed loop system. The solution is based on synthesizing specially defined class of control Lyapunov functions (CLFs) for switched systems, that yield switching controllers with a guaranteed minimum dwell time in each mode. Next, we use a CEGIS-based approach to iteratively solve the resulting quantified exists-forall constraints, and find a CLF. We introduce relaxations to guarantee termination, as well as heuristics to increase convergence speed. Finally, we evaluate our approach on a set of benchmarks ranging from two to six state variables. Our evaluation includes a preliminary comparison with related tools. The proposed approach shows the promise of nonlinear SMT solvers for the synthesis of provably correct switching control laws.

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    Tutorial introducing applications of the existing α,β-CROWN verifier to scalable formal verification of neural network controllers via bound computation and domain partitioning.

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