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Neuromorphic Computing with AER using Time-to-Event-Margin Propagation

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arxiv 2304.13918 v1 pith:EOKTN4CM submitted 2023-04-27 cs.NE

classification cs.NE
keywords computingneuromorphicnetworkneuralarchitecturesprotocolconventionalinterconnect
verification ladder T0 review T1 audit T2 compute T3 formal

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Address-Event-Representation (AER) is a spike-routing protocol that allows the scaling of neuromorphic and spiking neural network (SNN) architectures to a size that is comparable to that of digital neural network architectures. However, in conventional neuromorphic architectures, the AER protocol and, in general, any virtual interconnect plays only a passive role in computation, i.e., only for routing spikes and events. In this paper, we show how causal temporal primitives like delay, triggering, and sorting inherent in the AER protocol itself can be exploited for scalable neuromorphic computing using our proposed technique called Time-to-Event Margin Propagation (TEMP). The proposed TEMP-based AER architecture is fully asynchronous and relies on interconnect delays for memory and computing as opposed to conventional and local multiply-and-accumulate (MAC) operations. We show that the time-based encoding in the TEMP neural network produces a spatio-temporal representation that can encode a large number of discriminatory patterns. As a proof-of-concept, we show that a trained TEMP-based convolutional neural network (CNN) can demonstrate an accuracy greater than 99% on the MNIST dataset. Overall, our work is a biologically inspired computing paradigm that brings forth a new dimension of research to the field of neuromorphic computing.

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Cited by 1 Pith paper

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    A LIF-only SNN accelerator using differential time encoding reports 99.03% MNIST accuracy on FPGA and ASIC with no multiplication operations.

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