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A software decoder implementation for H.266/VVC video coding standard

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arxiv 2012.02832 v2 pith:EWCUDFFB submitted 2020-12-04 eess.IV

Bin Zhu , Shan Liu , Yuan Liu , Yi Luo , Jing Ye , Haiyan Xu , Ying Huang , Hualong Jiao
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Xiaozhong Xu Xianguo Zhang Chenchen Gu
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keywords standardvideocodingdecodercomplexityimplementationprocessingachieve
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Versatile Video Coding Standard (H.266/VVC) was completed by Joint Video Expert Team (JVET) of ITU-T and ISO/IEC, in July 2020. This new ITU recommendation/international standard is a successor to the well-known H.265/HEVC video coding standard with roughly doubled compression efficiency, but also at the cost of an increased computational complexity. The complexity of H.266/VVC decoder processing modules is studied in this paper. An optimized decoder implementation using SIMD instruction extensions and additional parallel processing including data and task level parallelism is presented, which can achieve real-time decoding of 4K 60fps VVC bitstreams on an x86 based CPU.

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