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REVIEW 4 major objections 4 minor 8 references

A Low Power Monolithic Active Pixel Sensor Prototype for the STCF Inner Tracker

T0 review · 4 major / 4 minor · reviewed 2026-08-07 · deepseek-v4-flash

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Pith's one-line read Large-pixel MAPS prototype reports 55.7 mW/cm2 and >99.9% detection efficiency for the STCF inner tracker.

desk verdict Genuine MAPS prototype with a smart low-power readout idea, but the suitability claim overreaches: timing is never measured and the simulated time walk exceeds the spec. read the letter →

arxiv 2506.01643 v1 pith:FJALKMXZ submitted 2025-06-02 physics.ins-det hep-ex

Dongwei Xuan , Ruiyang Zhang , Jiajun Qin , Hao Han , Xinyu Bin , Zihan Xu , Lei Zhao , Jianbei Liu
show 6 more authors
Liang Zhang Anqing Wang Aodong Song Xiangming Sun Le Xiao Lailin Xu
This is my paper
classification physics.ins-dethep-ex
keywords STCFMAPSpixelreadoutcircuitlowpowerconsumptionmonolithicactivesensorinnertrackertimestampdistributionlarge
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper argues that a monolithic active pixel sensor (MAPS) with deliberately stretched pixel electrodes can satisfy the two hardest requirements of the proposed Super Tau-Charm Facility (STCF) inner tracker: staying below the 100 mW/cm2 power budget while adding 50 ns timing information. The design cuts power not by shrinking circuits but by enlarging the pixels, which reduces the number of readout columns and therefore the dominant timestamp-distribution power. Simulations scaled to a full 2 cm by 2 cm chip give 55.7 mW/cm2, and prototype laser tests at about 1 MIP show detection efficiency above 99.9% for both sensor variants. A sympathetic reader would take the paper as showing that a large-pixel MAPS architecture is a credible candidate for the STCF ITK, provided the scaled power figure holds in real silicon.

What carries the argument

The load-bearing mechanism is the large-pixel 'column-drain' readout architecture. Pixel pitch is 31 µm by 170 µm, with the wide dimension along the row, so timestamp distribution power, which scales as $F_{clk} \cdot N_{col} \cdot C_{par} \cdot V_{DD}^2$, is reduced by cutting the number of columns $N_{col}$. Each pixel integrates an open-loop front-end (derived from ALPIDE, with a MALTA2-style cascode for the larger input capacitance) and priority readout logic that transfers only hit pixels' leading-edge and trailing-edge timestamps to the periphery at 10 MHz per column. The peripheral circuit handles timestamp correction, aggregation, framing, 8b/10b encoding, and serialization, with the full-scale power simulation done in PrimeTime PX after place-and-route.

What would settle it

Fabricate a 2 cm by 2 cm version of this architecture and measure its average power draw at the design hit rate: if it exceeds 100 mW/cm2, the paper's central low-power claim is disproved. Independently, a beam test with real minimum-ionizing particles scanning the full pixel surface would check whether detection efficiency stays above 99.9% outside the laser spot, especially at corners.

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Extended reading notes

Core claim

On the paper's own terms, the central discovery is that extending the sensor electrode laterally to 70-140 µm and connecting it either actively (stretched n-well) or by metal jumpers reduces the number of pixel columns per unit width enough to cut timestamp-distribution power from roughly 80 mW/cm2 (the reference small-pixel design) to 12.2 mW/cm2, giving a total simulated full-scale power of 55.7 mW/cm2. The active-connect Sensor D combines this low power with a fast charge collection (about 35 ns in the worst corner case), a uniform threshold of 319e- with 10.8e- dispersion, and laser-verified detection efficiency above 99.9% at an injected charge of 1600 e- (about 1 MIP). The paper frames this as validating the large-pixel approach for the STCF inner tracker.

Load-bearing premise

The full-scale power claim assumes that scaling the prototype's post-layout power simulation to a 2 cm by 2 cm chip, using PrimeTime PX, predicts the power of a real fabricated device; no full-scale silicon or direct power measurement is presented.

Editorial extensions

If this is right

  • If the scaled power simulation is accurate, a full 2x2 cm2 STCF ITK sensor would run at 55.7 mW/cm2, leaving margin under the 100 mW/cm2 cooling limit and enabling a lower material budget.
  • The 50 ns timestamp LSB meets the initial STCF timing requirement, so the same chip can provide time-of-arrival and time-over-threshold for pileup mitigation without a separate timing layer.
  • The two 800 Mbps LVDS links support event rates up to 8.7 MHz/cm2, more than ten times the innermost layer's average rate, so the readout will not be the bottleneck.
  • Sensor D (active-connect) appears preferable to Sensor B (metal-connect): similar power, faster charge collection, more uniform thresholds, and smaller efficiency loss at pixel edges.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • I would not treat the 55.7 mW/cm2 as a measured property until a full-scale chip is built and powered; the figure comes from scaling the prototype's post-layout simulation, so a real 2x2 cm2 chip could exceed the limit if clock distribution or IR-drop effects were underestimated.
  • The laser test is a proxy for ionizing particles, not a beam test; a real minimum-ionizing-particle beam could reveal edge or corner inefficiencies that the focused infrared spot misses.
  • The large-pixel trade deliberately gives up spatial resolution (170 µm pitch) in exchange for power; that is fine for STCF's relaxed 100 µm requirement, but the same design would not transfer to a vertex detector needing fine position.
  • Reaching the 20 ns timing goal would likely require a higher timestamp clock or a different distribution scheme, which would push power back up; the paper only demonstrates the 50 ns LSB.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 4 minor

Summary. The paper reports the design and preliminary characterization of CharTPix-TJ-v0.1, a monolithic active pixel sensor prototype for the STCF inner tracker. To reduce the power cost of timestamp distribution, the design uses laterally extended collection electrodes (active-connect and metal-connect sensor variants, B and D) with a column-drain readout. The paper presents TCAD-based sensor simulations, a front-end architecture derived from ALPIDE with ToA/ToT capability, and a full-scale power projection of 55.7 mW/cm2 obtained by scaling the prototype design to 2 cm x 2 cm in a PrimeTime PX simulation. Measured results include threshold and ENC distributions from charge-injection tests and infrared-laser efficiency maps, with the claim of >99.9% detection efficiency at approximately 1 MIP for both sensor types. The conclusion states that the prototype's performance validates its suitability for the STCF ITK.

Significance. If the reported results hold, the large-pixel MAPS architecture is a credible route toward the STCF ITK requirements of <100 mW/cm2 power and 50 ns timing resolution. The paper's strengths are that it presents a fabricated prototype, includes both electrical and laser-based measurements, and gives a transparent power breakdown with a specific simulation tool. The main significance lies in the architectural idea of reducing the number of columns by increasing pixel pitch in one direction, which is well motivated and quantified in the timestamp-distribution power formula. However, the central power claim is a simulation projection, and the timing performance—one of the two stated requirements—is not measured at all. The efficiency measurement at ~1 MIP is also reported without the corresponding map or uncertainty statement. These gaps prevent the paper from fully supporting the suitability claim, but they are addressable in revision.

major comments (4)
  1. [Section 4 and Section 3.1] The paper claims in the abstract that the design meets the 'required spatial and timing resolutions' and in the conclusion that the sensors are 'validated suitability for the target application,' yet no timing measurement appears anywhere in Section 4. The only timing quantity reported in the paper is a simulated time walk of less than 320 ns for Sensor B (Section 3.1), which is more than six times the initial 50 ns STCF timing requirement stated in Section 1. The ToA LSB of 50 ns is a bin size, not a resolution; jitter, threshold dispersion, and time walk all contribute. The laser test in Section 4.2 uses a 'specified time window' for valid detection, but the window width is never quantified. This is a load-bearing missing-evidence gap for the suitability claim and must either be filled with measured timing data or the claim must be explicitly softened to exclude timing.
  2. [Section 4.1, Figures 5(a) and 6(a)] The quoted Sensor B performance numbers—mean threshold 312 e-, threshold dispersion 16.5 e-, and average ENC 17.9 e-—are computed from even-numbered columns only. The full-array threshold distribution shown in Figure 5(a) is bimodal with mean 430 e- and standard deviation 137 e-. The odd-even inconsistency is attributed to parasitic coupling of the PULSE injection signal and is said to be validated by the laser test, but the text does not report the even/odd separated statistics or the full-array values alongside the even-column values. Since the conclusion directly compares Sensor B and Sensor D using these numbers, the manuscript should report both the full-array and the selected-column values, and the conclusion should carry the qualification that the Sensor B figures are for a subset of columns.
  3. [Section 3.2 and Abstract] The headline full-scale power consumption of 55.7 mW/cm2 is a simulation extrapolation, not a measurement. Section 3.2 states that the analysis was performed 'under the hypothesis of scaling the prototype design to a dimension of 2 cm x 2 cm' using PrimeTime PX on a placed-and-routed peripheral circuit. No measured power consumption of the prototype is reported. The scaling assumption—that the post-layout simulation of a scaled prototype predicts the power of a real full-size chip—is load-bearing for the central low-power claim. The abstract and conclusion should clearly label this as a simulation-based projection, and any measured prototype power should be reported for comparison.
  4. [Section 4.2 and Figure 7] The efficiency claim of 'average charge collection efficiency exceeding 99.9%' at approximately 1 MIP is stated in the text and conclusion, but the efficiency maps shown in Figure 7 correspond to a laser intensity calibrated to 600 e- (<0.4 MIP), not to the 1600 e- (~1 MIP) level. No map or numerical distribution at 1600 e- is provided. In addition, the calibration of laser intensity to 600 e- and 1600 e- uses the threshold extracted from the same S-curve measurement, making the charge scale self-referential. Please provide the 1600 e- efficiency maps, the number of laser pulses per point, and the statistical uncertainty on the 99.9% value.
minor comments (4)
  1. [Section 1] There are typos: 'extremly' should be 'extremely' and 'effciency' should be 'efficiency' in Section 4.2.
  2. [Section 3.1] The simulated threshold (314 e-) and ENC (11 e-) for Sensor B are presented without comparison to the measured values in the same section; a small table comparing simulation and measurement for both sensors would improve clarity.
  3. [Section 4.2] The term 'specified time window' is used to define a valid detection, but its width is never given. Please state the window and, ideally, relate it to the 50 ns timing target.
  4. [Figure 5] The histograms in Figure 5 are labeled 'Calibrated,' but the calibration procedure (injection capacitance value, number of pixels, and fit function) is not described in the text; a brief description would help reproducibility.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the power and efficiency claims rest on simulations and measurements with standard calibrations, not on self-referential reasoning.

full rationale

The paper's central quantitative claims are a simulated full-scale power consumption of 55.7 mW/cm2 and a laser-measured detection efficiency exceeding 99.9% at about 1 MIP. The power figure is produced by place-and-route and PrimeTime PX simulation after scaling the prototype to 2 cm x 2 cm; it is a forward simulation under stated assumptions, not a parameter fitted to the claimed result. The laser intensity is calibrated by matching the intensity that gives 50% detection efficiency to the independently measured threshold charge, which is a standard calibration procedure, not a definitional circularity. The efficiency value at 1600 e- is then measured against this calibrated scale and is not equivalent to the calibration input. The design draws on prior chips such as ALPIDE and MALTA2, but these are external design references, not self-citations carrying the load of the paper's new claims. No uniqueness theorem or self-citation chain forces the architecture. The paper does omit any measured timing resolution and the only reported simulated time walk of under 320 ns for Sensor B is harder to reconcile with the 50 ns STCF requirement, but that is a missing-evidence and correctness concern, not circularity. Accordingly, no circular step is identified and the score is 0.

Assumptions & free parameters 3 free parameters · 5 assumptions · 0 invented entities

The central claims rest on measured prototype data plus simulated full-scale extrapolation. The most important unverified inputs are the scaling hypothesis for power and the injection-crosstalk explanation for Sensor B's odd-even pattern. There are no fitted physics parameters in the usual sense; design choices are listed under free_parameters.

free parameters (3)
  • Pixel pitch and collection electrode dimensions = 31 um x 170 um; 70 um and 140 um electrode widths
    Hand-chosen geometry to reduce column count and timestamp distribution power; not optimized from data (Section 2).
  • ToA/ToT least significant bit = 50 ns
    Design choice for timing binning; timing resolution is not measured in this paper.
  • Substrate bias = -6 V
    Operating point for all quoted measurements, chosen to lower detector capacitance (Section 2).
assumptions (5)
  • domain assumption STCF ITK target requirements (material budget <0.3% X0/layer, hit rate 1 MHz/cm2, TID 10 kGy/year, NIEL 1e11 n/cm2/year, timing 50 ns goal) are accepted as design drivers.
    Taken from STCF CDR and background studies [1,2]; not independently re-derived in this paper.
  • ad hoc to paper Full-scale chip power can be inferred from post-layout simulation of a scaled prototype using PrimeTime PX.
    Section 3.2 states power analysis was conducted 'under the hypothesis of scaling the prototype design to a dimension of 2 cm x 2 cm'; no full-scale hardware exists.
  • domain assumption TCAD models of the sensor structures correctly predict depletion, charge collection, and capacitance.
    Section 2 uses TCAD to compare sensors and to motivate substrate biasing; no direct experimental verification of the TCAD numbers is given.
  • ad hoc to paper The odd-even threshold inconsistency in Sensor B is caused by parasitic coupling of the PULSE injection signal, not by the sensor or front-end.
    Section 4.1 calls this a hypothesis ('hypothesized to originate') and uses it to justify reporting even-column-only results for Sensor B.
  • domain assumption Laser intensity calibrated to threshold at the pixel center yields the stated MIP-equivalent charges across the pixel area.
    Section 4.2 describes the calibration method; no independent charge measurement is available to verify the 600e- and 1600e- levels.

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Cite this review

Pith. "Pith review of A Low Power Monolithic Active Pixel Sensor Prototype for the STCF Inner Tracker." pith.science (2026). https://pith.science/paper/FJALKMXZ

@misc{pith2026250601643,
  author       = {Pith},
  title        = {Pith review of: A Low Power Monolithic Active Pixel Sensor Prototype for the STCF Inner Tracker},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/FJALKMXZ}},
  note         = {Machine review of arXiv:2506.01643}
}
abstract

The Super Tau-Charm Facility (STCF) is a proposed $e^+e^-$ collider with a peak luminosity 100 times higher than that of the present tau-charm factory. The inner tracker (ITK) of STCF should feature a low material budget and high readout speed. Under these requirements, the monolithic active pixel sensor (MAPS) is considered as a promising candidate for the ITK. To minimize the power consumption of MAPS (for low material budget), larger-size sensors are proposed to reduce the scale of the readout circuitry while preserving the required position resolution. Multiple sensors with varying dimensions and structures were designed and integrated in several prototype chips for performance comparison, fabricated in a 180~nm CIS process. The in-pixel readout circuit can also provide time of arrival (ToA) and time-over-threshold (ToT) of the hit signal, with a least significant bit (LSB) of 50 ns. The peripheral readout circuit performs operations including timestamp correction, data aggregation, caching, framing, 8b/10b encoding, and serialization. According to simulation, the power consumption for a full-scale chip is about 55.7 mW/cm2. Preliminary measurements have been conducted on the prototype chips.

Figures

Figures reproduced from arXiv: 2506.01643 by the authors.

Figure 1
Figure 1. Sensor structures: (a) small sensor as a reference, (b) metal-connect [PITH_FULL_IMAGE:figures/full_fig_p004_1.png] view at source ↗
Figure 4
Figure 4. Test system for MAPS prototypes Threshold Distribution Calibrated Entries 419 Mean 430.1 Std Dev 137.1 200 300 400 500 600 700 800 900 - e 0 5 10 15 20 25 30 35 40 45 Entries Threshold Distribution Calibrated Entries 419 Mean 430.1 Std Dev 137.1 Threshold Distribution Calibrated (a) Temporal Noise Distribution Calibrated Entries 419 Mean 17.34 Std Dev 2.054 0 10 20 30 40 50 60 70 80 90 100 - e 0 10 20 30 40 50 60 En… view at source ↗
Figure 5
Figure 5. (a) Threshold distribution of Sensor B, (b) ENC distribution of Sensor [PITH_FULL_IMAGE:figures/full_fig_p005_5.png] view at source ↗
Figures from the paper (2 more)
Figure 6
Figure 6. Figure 6: (a) Threshold map of Sensor B, (b) Threshold map of Sensor D [PITH_FULL_IMAGE:figures/full_fig_p006_6.png]
Figure 7
Figure 7. Figure 7: (a) Efficiency map of Sensor B, (b) Efficiency map of Sensor D from charge injection circuit rather than the front-end circuit itself. This was subsequently validated through the laser test. When evaluating only the even-numbered columns, the aver￾age threshold is meas…

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