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ECOLogic: Enabling Circular, Obfuscated, and Adaptive Logic via eFPGA-Augmented SoCs

T0 review · 5 major / 5 minor · reviewed 2026-08-05 · deepseek-v4-flash

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Pith's one-line read ECOLogic claims that embedding a small eFPGA fabric inside an ASIC, guided by the ECOScore partitioning rule, preserves roughly 90% of ASIC performance while adding FPGA-style reconfigurability, security redaction, and dramatic deployment-c

desk verdict A sensible eFPGA-in-ASIC idea with good literature grounding, but the headline performance/carbon/power numbers are not credible as presented. read the letter →

arxiv 2508.04516 v1 pith:FPJ7LK35 submitted 2025-08-06 cs.AR cs.ET

Ishraq Tashdid , Dewan Saiham , Nafisa Anjum , Tasnuva Farheen , Sazadur Rahman This is my paper
classification cs.ARcs.ET
keywords eFPGAASIC/FPGAhybridIPredactionhardwaresecuritycarbonfootprintreconfigurablelogicSystem-on-Chipcircularcomputing
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper claims the ASIC-versus-FPGA trade-off is avoidable: by embedding a small, lightweight FPGA fabric inside an otherwise hardened ASIC, and by using a scoring rule called ECOScore to decide which logic blocks go into the fabric, a chip can keep most of the ASIC's speed while gaining the FPGA's post-fabrication flexibility. Reported results across six SoC modules show the hybrid holding roughly 90% of ASIC clock speed (about 1.8–2.2 GHz vs. 2.07–2.53 GHz for the ASIC and 0.125 GHz for the FPGA), 9.8 ns timing slack versus 5.1 ns for the FPGA, and about 480× lower power than a full FPGA implementation. The paper further argues that because the same silicon is reused across applications, deployment-phase carbon falls by about 99.7% relative to FPGA-only designs, a 300–500× reduction. The mechanism is selective reconfiguration: stable logic stays hardened in ASIC, while volatile, security-sensitive, or aging-prone logic is mapped to eFPGA tiles and can be updated or remapped after fabrication.

What carries the argument

ECOScore, a four-term convex scoring rule, $\mathrm{ECOScore}_i = \alpha A_i + \beta O_i + \gamma P_i + \delta R_i$, where adaptability is log-scaled RTL churn, piracy threat is a weighted mix of confidentiality, I/O exposure, and redaction coverage, performance tolerance is the frequency-drop ratio between ASIC and eFPGA, and resource fit is an inverse-area normalization. This score chooses which IPs to move into the eFPGA fabric and therefore carries the entire selective-reconfiguration argument. A second load-bearing mechanism is the deployment-phase carbon model $C_{\mathrm{ECOLogic}} = \sum_{i=1}^{N_{\mathrm{app}}} T_i \cdot C_{\mathrm{deploy},i}$, which sums runtime and development emi

What would settle it

Re-run the carbon model with the FPGA baseline also allowed five application reuses, keeping all other parameters from Table II fixed; if the FPGA's per-application carbon drops to the same order as ECOLogic's, the 99.7% claim is an artifact of asymmetric accounting. Alternatively, fabricate the six benchmark designs as an ECOLogic chip and as an equivalent ASIC; measured power and clock speeds that do not approach the ASIC's within the reported margins would falsify the near-ASIC performance and 480× power claims.

Watch

Extended reading notes

Core claim

ECOLogic's central claim is that a small amount of reconfigurable fabric embedded in an ASIC can absorb exactly the logic that would otherwise force full re-fabrication or an FPGA's performance penalty. The paper introduces ECOScore, a four-term weighted score (adaptability, piracy threat, performance tolerance, resource fit) that ranks IP blocks for eFPGA mapping; in the evaluation, cryptographic cores score highest and are moved wholly into the fabric, while large AI accelerators score lower on area fit and are better candidates for partial reconfiguration. The reported outcome is near-ASIC performance—clock speeds of 1.8–2.2 GHz against 2.07–2.53 GHz for hardened ASIC and 0.125 GHz for FP

Load-bearing premise

The headline carbon and power comparisons charge ECOLogic only deployment-phase emissions with five applications per chip and zero configuration time, while the FPGA baseline gets no multi-application reuse; under symmetric accounting the 99.7% carbon reduction and the 480× power advantage would not hold as stated.

Editorial extensions

If this is right

  • A single ECOLogic chip can host successive generations of an application by reconfiguring only the fabric region, avoiding the carbon cost of new tape-outs.
  • Systems that currently use FPGAs for post-fab flexibility could run at near-ASIC speed and roughly 480× lower power, if only the modules that actually need it are made reconfigurable.
  • Sensitive IP moved into the fabric is hidden until a trusted bitstream configures it, giving design houses a post-fab defense against untrusted-foundry reverse engineering.
  • Thermal and aging degradation can be countered by remapping critical paths to healthier fabric regions, extending useful chip lifetime.
  • The same silicon can be repurposed across applications (e.g., cryptographic to AI workloads), converting a linear 'manufacture, deploy, discard' lifecycle into a reuse-based circular model.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The 99.7% carbon reduction assumes ECOLogic is reused across five applications while the FPGA baseline is not; allowing the FPGA the same reuse would shrink the reported gap substantially, so the headline is sensitive to the accounting boundary.
  • The ECOScore weights used in the study (0.25 adaptability, 0.35 piracy threat, 0.20 performance tolerance, 0.20 resource fit) favor security and flexibility; designers targeting minimum power would weight differently and send different IPs to the fabric, shifting the area/power trade-off.
  • The aging-remapping result implies a runtime health monitor that reconfigures when slack degrades, but the paper only evaluates static remapping at temperature points; a closed-loop, on-chip remapping controller is a natural next step.
  • The Design 5 outlier shows the sustainability benefit is not universal: there is a design-dependent threshold in fabric footprint and dynamic power below which ECOLogic is carbon-positive; finding that threshold would turn the framework into a predictive tool.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

5 major / 5 minor

Summary. The paper proposes ECOLogic, a hybrid SoC architecture that embeds lightweight eFPGA fabric in an otherwise ASIC-style design, together with ECOScore, a weighted scoring framework to decide which IPs should be mapped to reconfigurable logic. The authors evaluate six IPs (crypto, AI accelerators, an interconnect, and a controller) and report near-ASIC clock speeds, 16× frequency improvement over FPGA, 480× lower power, a 9.8 ns timing slack, a 99.7% carbon-footprint reduction, and improved aging resilience through dynamic remapping. The manuscript also discusses security benefits of eFPGA-based logic redaction and a circular-economy lifecycle view.

Significance. The underlying architectural direction—selective eFPGA augmentation of ASICs guided by quantitative criteria—is timely and plausible, and the ECOScore framework is a reasonable heuristic that could help designers make partitioning decisions. The paper also connects to sustainability and circularity in a way that most prior ASIC/eFPGA hybrid work does not. However, the quantitative evidence currently supplied does not support the headline claims. The carbon analysis uses asymmetric accounting that strongly favors ECOLogic, the power and area numbers lack any described measurement or estimation methodology, and there are internal inconsistencies in the central scoring table. The ECOScore formulas are self-contained heuristics and are not used to fit the performance results, so there is no derivation-equals-input circularity; the problem is that the reported sustainability savings are largely an arithmetic consequence of chosen inputs (Napp=5, deployment-only emissions, zero configuration time). If the evaluation were made symmetric, inclusive, and reproducible, the paper would make a useful contribution.

major comments (5)
  1. [Sec. IV-B, Eqs. (7)–(8), Table II] The lifecycle boundary is asymmetric and determines the headline carbon result. Eq. (7) charges ECOLogic only deployment-phase emissions because 'hardware is manufactured once,' and Table II gives ECOLogic Napp=5 applications per chip and Config time=0. The FPGA baseline in Table IV is charged per-application with no multi-application reuse and no equivalent amortization. Under this accounting, the 99.7% reduction is built into the model, not demonstrated. The omitted embodied/manufacturing carbon is especially significant given the ECOLogic die area of 7,219 mm² reported in Fig. 7. A symmetric lifecycle comparison—including manufacturing and deployment emissions for both platforms and identical reuse assumptions—is required before the sustainability claim can be assessed.
  2. [Sec. V-C, Table IV] The 'average 99.68% reduction' is computed over Designs 1–4 and 6 only, as the text admits, and Design 5 is excluded because ECOLogic has 2.6× higher deployment cost than FPGA at 1-year lifetime (3.24K vs 1.24K). The abstract and conclusion state 'across six diverse SoC modules' and a 99.7% reduction without this caveat, which is misleading. Also, Table IV's units are unclear: the column header says '×10^4', but the row entries (e.g., 4.66, 1.49K) and the text's phrase 'drops from 1.49K to 4.66×10^4 kg CO2' are contradictory. The table and the derived ratios must be reconciled.
  3. [Sec. V-E, Fig. 7] The 480× power claim rests on a single pair of numbers (52 mW vs 25,000 mW) with no power-estimation methodology: no technology library, synthesis tool version, toggle rates, clock gating assumptions, or per-design power breakdown are reported. A 52 mW total power for a 7,219 mm² die is not credible without further evidence. Similarly, the 9.8 ns slack and 2.0 GHz frequency are reported without specifying the critical path, operating conditions, or how the eFPGA and ASIC domains were analyzed. Please provide the synthesis/PowerCompiler logs or a detailed methodology, and report per-design power, area, and slack.
  4. [Sec. V-B, Table III] The ECOScore values in the text do not match Table III. For example, Design 3 is listed with A3=1.00 in Table III but 0.93 in the text; Design 1 is 0.98 vs 0.91; Design 2 is 0.82 vs 0.76. The final ECOScore column in Table III is {0.86, 0.84, 0.72, 0.75, 0.64, 0.67}, while the text reports normalized values {1.00, 0.98, 0.84, 0.87, 0.74, 0.78}. Since ECOScore is the central selection mechanism, these inconsistencies make the framework non-reproducible and must be resolved.
  5. [Sec. V-D, Fig. 5] The aging analysis claims ECOLogic maintains >5 ns timing slack at 130°C 'by leveraging its ability to dynamically remap logic from thermally stressed, degraded regions to higher-performing, idle regions.' No experiment, simulation, or measurement is described that supports this claim. The curves appear illustrative rather than derived from data. Either provide the experimental setup and results, or clearly label this as a conceptual/expected behavior rather than a measured outcome.
minor comments (5)
  1. [Eqs. (2)–(5)] The symbol Ri is used for two different quantities: redaction potential in Eqs. (2)–(3) and resource fit in Eq. (5). This creates confusion in Table III, where 'R' appears in both the Obfus. and Resrc. columns.
  2. [Table II] 'HLS synthesis time' is listed, but the design flow uses Yosys RTL synthesis; there is no HLS flow described. Please align terminology or add the HLS step.
  3. [Sec. V-A] 'CV A6 Interconnect' is not defined; if it is a version or product name, a reference is needed.
  4. [Eq. (7)] Eq. (7) uses Cdeploy,i while Eq. (8) defines Cdeploy without a subscript; use consistent notation.
  5. [Sec. V-C] The phrase '1.49K to 4.66×10^4 kg CO2' is a likely typo; based on Table IV, the intended comparison appears to be 1.49K to 4.66 (kg CO2), a reduction. The text should match the table.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity; ECOLogic's performance and sustainability figures are empirical/model outputs with transparent assumptions, not definitional identities that force the conclusions.

full rationale

The derivation chain is not circular. ECOScore (Eqs. 1-6) is an explicit heuristic used only to rank IPs; its four submetrics are defined from RTL churn, I/O exposure, synthesized frequency ratio, and area, and none of these definitions presuppose the later performance or carbon results. The performance comparisons (Sec. V-E) and the 90% retention / 9.8 ns slack / 480x power figures are presented as implementation results, not as consequences of the ECOScore formulas. The carbon-footprint claims are produced by a transparent parametric model (Eqs. 7-8, Table II): given the stated deployment-only scope, Napp=5, Nvol=1e6, and the cited GreenFPGA/ECO-CHIP parameters, the 300-500x reduction follows arithmetically. That is model output, not a hidden identity: the reduction would change if the inputs changed, and the paper does not conceal the assumptions. The choice to exclude manufacturing emissions and set Config time=0 is a model-boundary choice; it may be questioned on fairness grounds, but it is not a case of defining the conclusion into existence. Similarly, dropping Design 5 from the average (Sec. V-C) is selective reporting, not circular reasoning. The self-citations ([6], [29], [30], [33]) are background/peripheral and do not carry the central argument. No equation equals another by construction, and no fitted parameter is relabeled as a prediction.

Assumptions & free parameters 8 free parameters · 5 assumptions · 0 invented entities

The central quantitative claims rest on designer-chosen weights and carbon-model inputs. The ECOLogic architecture itself uses established components (eFPGA fabric and ASIC), but the reported power and carbon numbers are arithmetic consequences of the parameters in Table II and the power/frequency estimates, not independently measured results.

free parameters (8)
  • ECOScore weights (alpha, beta, gamma, delta) = (0.25, 0.35, 0.20, 0.20)
    Designer-chosen convex weights in Eq. (6) that directly determine which IPs are recommended for eFPGA mapping; Table III results follow from these weights.
  • Obfuscation sub-weights (mu, nu, xi) = (0.5, 0.3, 0.2)
    Weights in Eq. (3) chosen by the authors for the piracy-threat score; not derived from data.
  • Napp (number of applications per ECOLogic chip) = 5
    Table II assumes each ECOLogic chip is reused across five applications; the FPGA comparator is not given the same reuse, which drives the 99.7% reduction.
  • Nvol (deployment volume) = 1,000,000
    Table II sets deployment volume to 1e6; absolute carbon numbers scale linearly with this parameter.
  • T (runtime per application) = 131,400 hours (15 years)
    Table II input; deployment energy is T times power, so total carbon scales with this assumption and conflicts with the 0.2-2.5 year values in Table IV.
  • Grid carbon intensity C_src,use = 0.7 kgCO2/kWh
    Table II input taken from [13], no sensitivity analysis.
  • CPU power per core and synthesis times = 10 W, 2.5h RTL + 1.0h HLS, 8 cores
    Table II inputs for C_app-dev; these values determine the application-development carbon term.
  • Configuration time = 0 hours
    Table II sets bitstream reconfiguration time to zero, eliminating reconfiguration energy from the carbon model.
assumptions (5)
  • domain assumption Only universal (reconfigurable) circuits can preserve IP confidentiality with limited overhead.
    Sec. II-A cites Beerel et al. [18] for this formal result and uses it to justify eFPGA-based redaction, but no attack evaluation is performed in this paper.
  • domain assumption eFPGA mapping can redact sensitive logic and prevent reverse engineering or overproduction.
    Sec. IV-A1 asserts this based on prior redaction literature [39] without new security experiments or attack simulations.
  • ad hoc to paper Aging and thermal stress can be mitigated by remapping logic to healthier eFPGA regions.
    Sec. V-D and Fig. 5 assume dynamic remapping restores timing slack, but no aging model, fault model, or remapping experiment is presented.
  • ad hoc to paper Deployment-phase-only carbon accounting is the correct comparison metric for ECOLogic versus FPGA.
    Eq. (7) excludes manufacturing and embodied carbon of the eFPGA fabric for ECOLogic; this assumption underlies the 99.7% result.
  • ad hoc to paper The FPGA baseline is single-application while ECOLogic is reused across Napp=5 applications.
    Implicit in Table IV and Eq. (7); FPGAs are also reconfigurable and could be reused, so this asymmetry favors ECOLogic.

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Cite this review

Pith. "Pith review of ECOLogic: Enabling Circular, Obfuscated, and Adaptive Logic via eFPGA-Augmented SoCs." pith.science (2026). https://pith.science/paper/FPJ7LK35

@misc{pith2026250804516,
  author       = {Pith},
  title        = {Pith review of: ECOLogic: Enabling Circular, Obfuscated, and Adaptive Logic via eFPGA-Augmented SoCs},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/FPJ7LK35}},
  note         = {Machine review of arXiv:2508.04516}
}
read the original abstract

Traditional hardware platforms - ASICs and FPGAs - offer competing trade-offs among performance, flexibility, and sustainability. ASICs provide high efficiency but are inflexible post-fabrication, require costly re-spins for updates, and expose IPs to piracy risks. FPGAs offer reconfigurability and reuse, yet suffer from substantial area, power, and performance overheads, resulting in higher carbon footprints. We present ECOLogic, a hybrid design paradigm that embeds lightweight eFPGA fabric within ASICs to enable secure, updatable, and resource-aware computation. Central to this architecture is ECOScore, a quantitative scoring framework that evaluates IPs based on adaptability, piracy threat, performance tolerance, and resource fit to guide RTL partitioning. Evaluated across six diverse SoC modules, ECOLogic retains an average of 90 percent ASIC-level performance (up to 2 GHz), achieves 9.8 ns timing slack (versus 5.1 ns in FPGA), and reduces power by 480 times on average. Moreover, sustainability analysis shows a 99.7 percent reduction in deployment carbon footprint and 300 to 500 times lower emissions relative to FPGA-only implementations. These results position ECOLogic as a high-performance, secure, and environmentally sustainable solution for next-generation reconfigurable systems.

Figures

Figures reproduced from arXiv: 2508.04516 by the authors.

Figure 1
Figure 1. Comparison of ASIC, FPGA, and ECOLogic (ours) across five metrics. To address the rigidity, obsolescence, and secu￾rity challenges of conven￾tional hardware, this pa￾per proposes ECOLogic, a hybrid System-on-Chip (SoC) architecture that embeds eFPGA fabrics within an ASIC frame￾work. Inspired by the principles of engineering change, ECOLogic extends tradi￾tional ECO practices into the post-fab domain through dy￾nami… view at source ↗
Figure 2
Figure 2. eFPGA fabric architecture and its fundamental components. (a) A conceptual illustration of a 4 × 4 eFPGA fabric, highlighting the internal elements of each tile. (b) A detailed view of the Configuration Logic Block (CLB) within a tile, comprising LUTs, FFs, and multiplexers. without full re-synthesis or re-layout [9, 23]. However, they are limited to predefined regions and often induce routing congestion or timing v… view at source ↗
Figure 3
Figure 3. ECOLogic design flow for sustainable computing illustrating the RTL implementation, selection of security, accelerator or dynamic IP for eFPGA configuration, and fabricating to physical SoC. Ai = ln(1 + LOC changedi ) ln(1 + maxj LOC changedj ) (1) where LOC changedi denotes the line-of-code changes for IP i. The logarithmic normalization tempers extreme differ￾ences and avoids biasing against smaller blocks that na… view at source ↗
Figures from the paper (4 more)
Figure 4
Figure 4. Figure 4: Lifecycle flow of semiconductor systems across three design paradigms. ECOLogic uniquely enables circularity via in-field and cross￾product reconfiguration, allowing components to be reused, repaired, or repurposed after deployment—capabilities not available in traditi…
Figure 5
Figure 5. Figure 5: shows the temperature-induced timing slack degrada￾tion across ASIC, FPGA, and ECOLogic. Below 60◦C, all platforms maintain stable slack (> 8 ns), indicating minimal [PITH_FULL_IMAGE:figures/full_fig_p007_5.png]
Figure 6
Figure 6. Figure 6: compares the maximum clock speeds across ASIC, FPGA, and ECOLogic implementations for six IPs. FPGA designs consistently operate at just 0.125 GHz across all workloads, reflecting the inherent performance limitations of general-purpose reconfigurable logic. In contrast…
Figure 7
Figure 7. Figure 7: Comparison of Area, Power, Timing Slack, and Frequency for ECOLogic and FPGA. these values—ranging from 1.80 GHz to 2.20 GHz across the same designs. For instance, in the CNN accelerator, ECOLogic sustains 2.20 GHz, just 13% below ASIC and over 1600% faster than FPGA. …

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Reference graph

Works this paper leans on

42 extracted references · 41 canonical work pages · cited by 1 Pith paper

  1. [1]

    Towards the systematic reporting of the energy and carbon footprints of machine learning,

    P. Henderson et al., “Towards the systematic reporting of the energy and carbon footprints of machine learning,” J. Mach. Learn. Res. , vol. 21, no. 248, pp. 1–43, 2020

    work page 2020

  2. [2]

    The real climate and transformative impact of ict: A critique of estimates, trends, and regu- lations,

    C. Freitag et al., “The real climate and transformative impact of ict: A critique of estimates, trends, and regu- lations,” Patterns, vol. 2, no. 9, 2021

    work page 2021

  3. [3]

    On global electricity usage of communication technology: trends to 2030,

    A. S. G. Andrae et al., “On global electricity usage of communication technology: trends to 2030,” Challenges, vol. 6, no. 1, pp. 117–157, 2015

    work page

  4. [4]

    Asics versus fpgas: A comparison of fixed- function and reconfigurable architectures,

    F. J. Bartos, “Asics versus fpgas: A comparison of fixed- function and reconfigurable architectures,” Control Eng., vol. 52, no. 6, pp. 46–51, 2005

    work page 2005

  5. [5]

    Act: Designing sustainable computer systems with an architectural carbon modeling tool,

    U. Gupta et al., “Act: Designing sustainable computer systems with an architectural carbon modeling tool,” in Proceedings of the 49th Annual International Symposium on Computer Architecture, 2022, pp. 784–799

    work page 2022

  6. [6]

    Safe-sip: Secure authentication framework for system-in-package using multi-party computation,

    I. Tashdid, T. Farheen, and S. Rahman, “Safe-sip: Secure authentication framework for system-in-package using multi-party computation,” in Proceedings of the Great Lakes Symposium on VLSI 2025 , ser. GLSVLSI ’25. New York, NY , USA: Association for Computing Machinery, 2025, p. 391–396. [Online]. Available: https://doi.org/10.1145/3716368.3735248

    arXiv 2025

  7. [7]

    Evolute: evaluation of look-up-table- based fine-grained ip redaction,

    Guo, Rui et al.,, “Evolute: evaluation of look-up-table- based fine-grained ip redaction,” in 2023 Design, Au- tomation & Test in Europe Conference & Exhibition (DATE). IEEE, 2023, pp. 1–6

    work page 2023

  8. [8]

    Reliability evaluation and analysis of fpga- based neural network acceleration system,

    D. Xu et al., “Reliability evaluation and analysis of fpga- based neural network acceleration system,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , vol. 29, no. 3, pp. 472–484, 2021

    work page 2021

Show all 42 references
  1. [9]

    Eco timing optimization using spare cells and technol- ogy remapping,

    K.-H. Ho, Y .-P. Chen, J.-W. Fang, and Y .-W. Chang, “Eco timing optimization using spare cells and technol- ogy remapping,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 5, pp. 697–710, 2010

    2010

  2. [10]

    Engineering change order for combinational and sequential design rectification,

    J.-H. R. Jiang et al., “Engineering change order for combinational and sequential design rectification,” in Proc. Des. Autom. Test Eur. Conf. Exhib. (DATE). IEEE, 2020, pp. 726–731

    2020

  3. [11]

    Tehranipoor et al., Advances in logic locking

    M. Tehranipoor et al., Advances in logic locking. Cham: Springer Nature Switzerland, 2024, pp. 53–142. [Online]. Available: https://doi.org/10.1007/978-3-031-58687-3 2

    2024 doi

  4. [12]

    The road not taken: efpga accelerators utilized for soc security auditing,

    M. M. M. Rahman et al., “The road not taken: efpga accelerators utilized for soc security auditing,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 43, no. 10, pp. 3068–3082, 2024

    2024

  5. [13]

    Eco-chip: Estimation of carbon footprint of chiplet-based architectures for sustainable vlsi,

    C. C. Sudarshan et al, “Eco-chip: Estimation of carbon footprint of chiplet-based architectures for sustainable vlsi,” in 2024 IEEE International Symposium on High- Performance Computer Architecture (HPCA) . IEEE, 2024, pp. 671–685

    2024

  6. [14]

    Greenfpga: Evaluating fp- gas as environmentally sustainable computing solutions,

    C. Choppali Sudarshan et al., “Greenfpga: Evaluating fp- gas as environmentally sustainable computing solutions,” in Proc. 61st ACM/IEEE Des. Autom. Conf. (DAC) . ACM, 2024

    2024

  7. [15]

    Fpga architectures: An overview,

    U. Farooq et al., “Fpga architectures: An overview,” Tree- Based Heterogeneous FPGA Archit. , pp. 7–48, 2012

    2012

  8. [16]

    Circularity for secure and sustainable products and materials,

    U. D. of Energy, “Circularity for secure and sustainable products and materials,” 2024, accessed: 2025-02-15. [Online]. Available: https://www.energy.gov/sites/default/files/2024-10/ circularity-for-secure-sustainable-products-materials-report. pdf

    2024

  9. [17]

    Defense-in-depth: A recipe for logic locking to prevail,

    M. T. Rahman et al, “Defense-in-depth: A recipe for logic locking to prevail,” Integration, vol. 72, pp. 39–57, 2020

    2020

  10. [18]

    Towards a formal treatment of logic locking,

    P. Beerel et al. , “Towards a formal treatment of logic locking,” Cryptology ePrint Archive , 2022

    2022

  11. [19]

    Recent attacks and defenses on fpga- based systems,

    J. Zhang et al, “Recent attacks and defenses on fpga- based systems,” ACM Transactions on Reconfigurable Technology and Systems (TRETS) , vol. 12, no. 3, pp. 1– 24, 2019

    2019

  12. [20]

    Arnold: An efpga-augmented risc- v soc for flexible and low-power iot end nodes,

    P. D. Schiavone et al, “Arnold: An efpga-augmented risc- v soc for flexible and low-power iot end nodes,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 4, pp. 677–690, 2021

    2021

  13. [21]

    Flexbex: A risc-v with a reconfigurable instruction extension,

    N. Dao et al, “Flexbex: A risc-v with a reconfigurable instruction extension,” in 2020 International conference on field-programmable technology (ICFPT) . IEEE, 2020, pp. 190–195

    2020

  14. [22]

    A security-aware and lut-based cad flow for the physical synthesis of hasics,

    Z. U. Abideen et al, “A security-aware and lut-based cad flow for the physical synthesis of hasics,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , vol. 42, no. 10, pp. 3157–3170, 2023

    2023

  15. [23]

    Reap what you sow: Spare cells for post-silicon metal fix,

    K.-H. Chang et al., “Reap what you sow: Spare cells for post-silicon metal fix,” in Proc. Int. Symp. Phys. Des. (ISPD), 2008, pp. 103–110

    2008

  16. [24]

    Eco optimization using metal- configurable gate-array spare cells,

    H.-Y . Chang et al., “Eco optimization using metal- configurable gate-array spare cells,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 32, no. 11, pp. 1722–1733, 2013

    2013

  17. [25]

    Trends in asic and fpga use in space missions and their impact on esa technol- ogy roadmaps,

    R. Boada Gardenyes, “Trends in asic and fpga use in space missions and their impact on esa technol- ogy roadmaps,” Tech. Rep., Universitat Polit `ecnica de Catalunya, 2011

    2011

  18. [26]

    In-flight reconfigurable fpga- based space systems,

    N. Montealegre et al., “In-flight reconfigurable fpga- based space systems,” in Proc. NASA/ESA Conf. Adapt. Hardw. Syst. (AHS). IEEE, 2015, pp. 1–8

    2015

  19. [27]

    Mixed signal asic controller for satellite medium power dc/dc converters,

    K. R. Skup et al., “Mixed signal asic controller for satellite medium power dc/dc converters,” in Proc. Int. Conf. Mixed Des. Integr. Circuits Syst. (MIXDES). IEEE, 2015, pp. 359–363

    2015

  20. [28]

    Survey on advances in broadband signal generation and processing of asic semiconductors for defense satellites,

    B.-H. Shim et al., “Survey on advances in broadband signal generation and processing of asic semiconductors for defense satellites,” J. Electromagn. Eng. Sci., vol. 24, no. 4, pp. 377–383, 2024

    2024

  21. [29]

    Opl4gpt: An application space exploration of optimal programming language for hardware design by llm,

    K. Tasnia and S. Rahman, “Opl4gpt: An application space exploration of optimal programming language for hardware design by llm,” in Proceedings of the 30th Asia and South Pacific Design Automation Conference , 2025, pp. 981–987

    2025

  22. [30]

    Veri- opt: Ppa-aware high-quality verilog generation via multi- role llms,

    K. Tasnia, A. Garcia, T. Farheen, and S. Rahman, “Veri- opt: Ppa-aware high-quality verilog generation via multi- role llms,” arXiv preprint arXiv:2507.14776 , 2025

    2025 arXiv

  23. [31]

    Ballast: Implementation of a large mp-soc on 22nm asic technology,

    A. Rautakoura et al., “Ballast: Implementation of a large mp-soc on 22nm asic technology,” in Proc. Euromicro Conf. Digit. Syst. Des. (DSD) . IEEE, 2022, pp. 276– 283

    2022

  24. [32]

    A mixed-signal risc-v signal analysis soc generator with a 16-nm finfet instance,

    S. Bailey et al., “A mixed-signal risc-v signal analysis soc generator with a 16-nm finfet instance,” IEEE J. Solid- State Circuits, vol. 54, no. 10, pp. 2786–2801, 2019

    2019

  25. [33]

    Leveraging pho- tonic interconnects for scalable and efficient fully homo- morphic encryption,

    D. Saiham, D. Wu, and S. Rahman, “Leveraging pho- tonic interconnects for scalable and efficient fully homo- morphic encryption,” arXiv preprint arXiv:2506.12962 , 2025

    2025 arXiv

  26. [34]

    Farahmandi et al., CAD for hardware security

    F. Farahmandi et al., CAD for hardware security . Springer, 2023

    2023

  27. [35]

    Hardware redaction via designer- directed fine-grained efpga insertion,

    P. Mohan et al, “Hardware redaction via designer- directed fine-grained efpga insertion,” in 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2021, pp. 1186–1191

    2021

  28. [36]

    Fabulous: An embedded fpga frame- work,

    D. Koch et al., “Fabulous: An embedded fpga frame- work,” in Proc. ACM/SIGDA Int. Symp. Field-Program. Gate Arrays (FPGA) , 2021, pp. 45–56

    2021

  29. [37]

    Top-down physical design of soft embedded fpga fabrics,

    P. Mohan, O. Atli, O. Kibar, M. Zackriya, L. Pileggi, and K. Mai, “Top-down physical design of soft embedded fpga fabrics,” in The 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays , 2021, pp. 1–10

    2021

  30. [38]

    Yosys-a free verilog synthesis suite,

    C. Wolf et al, “Yosys-a free verilog synthesis suite,” in Proceedings of the 21st Austrian Workshop on Micro- electronics (Austrochip), vol. 97, 2013

    2013

  31. [39]

    Exploring efpga-based redaction for ip protection,

    J. Bhandari et al, “Exploring efpga-based redaction for ip protection,” in 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD) , 2021, pp. 1–9

    2021

  32. [40]

    Trustguard: Standalone fpga-based security monitoring through power side-channel,

    T. Zhang, M. Tehranipoor, and F. Farahmandi, “Trustguard: Standalone fpga-based security monitoring through power side-channel,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems , vol. 32, no. 2, pp. 319–332, 2024

    2024

  33. [41]

    Evaluating the security of efpga- based redaction algorithms,

    A. Rezaei et al, “Evaluating the security of efpga- based redaction algorithms,” in Proceedings of the 41st IEEE/ACM International Conference on Computer- Aided Design , ser. ICCAD ’22. New York, NY , USA: Association for Computing Machinery, 2022. [Online]. Available: https:/...

    2022

  34. [42]

    A computational model of nbti and hot carrier injection time-exponents for mosfet reliability,

    H. Kufluoglu et al., “A computational model of nbti and hot carrier injection time-exponents for mosfet reliability,” J. Comput. Electron. , vol. 3, no. 3, pp. 165–169, 2004. [Online]. Available: https: //doi.org/10.1007/s10825-004-7038-9

    2004 doi

Pith tools

Reviewed August 5, 2026 · model on record in the stance chip above.