Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures | Paper Citation Record

Observation 3c55e579-f107-4e74-abcc-55ec52014908 · outbound

This paper cites A Survey of Transformers.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures A Survey of Transformers

Reference 1

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This paper cites PaLM: Scaling Language Modeling with Pathways.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures PaLM: Scaling Language Modeling with Pathways

Reference 2

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This paper cites Language Models are Few-Shot Learners.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures Language Models are Few-Shot Learners

Reference 3

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This paper cites Finetuned Language Models Are Zero-Shot Learners.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures Finetuned Language Models Are Zero-Shot Learners

Reference 4

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This paper cites QLoRA: Efficient Finetuning of Quantized LLMs.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures QLoRA: Efficient Finetuning of Quantized LLMs

Reference 5

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This paper cites LoRA: Low-Rank Adaptation of Large Language Models.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures LoRA: Low-Rank Adaptation of Large Language Models

Reference 6

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This paper cites Few-Shot Parameter-Efficient Fine-Tuning is Better and Cheaper than In-Context Learning.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures Few-Shot Parameter-Efficient Fine-Tuning is Better and Cheaper than In-Context Learning

Reference 7

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This paper cites Parameter-Efficient Transfer Learning for NLP.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures Parameter-Efficient Transfer Learning for NLP

Reference 8

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This paper cites PANTHER: A Programmable Architecture for Neural Network Training Harnessing Energy -Efficient ReRAM,.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures PANTHER: A Programmable Architecture for Neural Network Training Harnessing Energy -Efficient ReRAM,

Reference 9

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This paper cites Architectures and Circuits for Analog -memory-based Hardware Accelerators for Deep Neural Networks,.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures Architectures and Circuits for Analog -memory-based Hardware Accelerators for Deep Neural Networks,

Reference 10

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This paper cites On Endurance of Processing in (Nonvolatile) Memory,.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures On Endurance of Processing in (Nonvolatile) Memory,

Reference 11

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This paper cites X -Former: In- Memory Acceleration of Transformers,.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures X -Former: In- Memory Acceleration of Transformers,

Reference 12

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This paper cites Noise Injection Adaption: End -to-End ReRAM Crossbar Non-ideal Effect Adaption for Neural Network Mapping,.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures Noise Injection Adaption: End -to-End ReRAM Crossbar Non-ideal Effect Adaption for Neural Network Mapping,

Reference 13

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This paper cites Temperature -Resilient RRAM -Based In -Memory Computing for DNN Inference,.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures Temperature -Resilient RRAM -Based In -Memory Computing for DNN Inference,

Reference 14

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This paper cites Fault -Free: A Framework for Analysis and Mitigation of Stuck -at-Fault on Realistic ReRAM -Based DNN Accelerators,.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures Fault -Free: A Framework for Analysis and Mitigation of Stuck -at-Fault on Realistic ReRAM -Based DNN Accelerators,

Reference 15

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This paper cites Long live TIME: Improving lifetime for training -in- memory engines by structured gradient sparsification,.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures Long live TIME: Improving lifetime for training -in- memory engines by structured gradient sparsification,

Reference 16

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This paper cites In -datacenter performance analysis of a tensor processing unit.,.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures In -datacenter performance analysis of a tensor processing unit.,

Reference 17

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This paper cites TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning with Hardware Support for Embeddings.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning with Hardware Support for Embeddings

Reference 18

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This paper cites A survey of architectural approaches for improving GPGPU performance, programmability and heterogeneity,.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures A survey of architectural approaches for improving GPGPU performance, programmability and heterogeneity,

Reference 19

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This paper cites ISAAC: a convolutional neural network accelerator with in -situ analog arithmetic in crossbars.,.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures ISAAC: a convolutional neural network accelerator with in -situ analog arithmetic in crossbars.,

Reference 20

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This paper cites ReTransformer: ReRAM -based Processing-in-Memory Architecture for Transformer Acceleration,.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures ReTransformer: ReRAM -based Processing-in-Memory Architecture for Transformer Acceleration,

Reference 21

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This paper cites AccelTran: A Sparsity -Aware Accelerator for Dynamic Inference with Transformers,.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures AccelTran: A Sparsity -Aware Accelerator for Dynamic Inference with Transformers,

Reference 22

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This paper cites A Framework for Accelerating Transformer-Based Language Model on ReRAM -Based Architecture,.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures A Framework for Accelerating Transformer-Based Language Model on ReRAM -Based Architecture,

Reference 23

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This paper cites FTRANS: Energy -Efficient Acceleration of Transformers Using FPGA,.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures FTRANS: Energy -Efficient Acceleration of Transformers Using FPGA,

Reference 24

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Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures TransPIM: A Memory-based Acceleration via Software -Hardware Co -Design for Transformer,

Reference 25

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This paper cites HAIMA: A Hybrid SRAM and DRAM Accelerator -in- Memory Architecture for Transformer,.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures HAIMA: A Hybrid SRAM and DRAM Accelerator -in- Memory Architecture for Transformer,

Reference 26

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This paper cites H3D -Transformer: A Heterogeneous 3D (H3D) Computing Platform for Transformer Model Acceleration on Edge Devices,.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures H3D -Transformer: A Heterogeneous 3D (H3D) Computing Platform for Transformer Model Acceleration on Edge Devices,

Reference 27

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Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures SwiftTron: An efficient hardware accelerator for quantized transformers,

Reference 28

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Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures Prefix-Tuning: Optimizing Continuous Prompts for Generation

Reference 29

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Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures Exploring Versatile Generative Language Model Via Parameter-Efficient Transfer Learning

Reference 30

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Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures BitFit: Simple Parameter- efficient Fine-tuning for Transformer-based Masked Language-models,

Reference 31

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This paper cites A systematic methodology for characterizing scalability of DNN accelerators using SCALE-sim,.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures A systematic methodology for characterizing scalability of DNN accelerators using SCALE-sim,

Reference 32

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Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures Small Pitch, High Aspect Ratio Via -Last TSV Module,

Reference 33

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Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures System on integrated chips (SoIC(TM) for 3D heterogeneous integration,

Reference 34

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Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures 3D Packaging for Heterogeneous Integration,

Reference 35

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This paper cites An Overview of the Development of a GPU with Integrated HBM on Silicon Interposer,.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures An Overview of the Development of a GPU with Integrated HBM on Silicon Interposer,

Reference 36

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Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures https://ddr-phy.org/,

Reference 37

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This paper cites PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning,.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning,

Reference 38

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Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures FlashAttention-2: Faster Attention with Better Parallelism and Work Partitioning

Reference 39

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Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures Demystifying 3D ICs: the pros and cons of going vertical,

Reference 40

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Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures An overview of through-silicon-via technology and manufacturing challenges,

Reference 41

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This paper cites Florets for Chiplets: Data Flow -aware High - Performance and Energy -efficient Network -on-Interposer for CNN Inference Tasks,.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures Florets for Chiplets: Data Flow -aware High - Performance and Energy -efficient Network -on-Interposer for CNN Inference Tasks,

Reference 42

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This paper cites A Survey of Design and Optimization for Systolic Array - based DNN Accelerators,.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures A Survey of Design and Optimization for Systolic Array - based DNN Accelerators,

Reference 43

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Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures 8-bit Optimizers via Block-wise Quantization

Reference 44

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This paper cites HuggingFace's Transformers: State-of-the-art Natural Language Processing.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures HuggingFace's Transformers: State-of-the-art Natural Language Processing

Reference 45

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This paper cites SQuAD: 100,000+ Questions for Machine Comprehension of Text.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures SQuAD: 100,000+ Questions for Machine Comprehension of Text

Reference 46

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This paper cites DNN+NeuroSim V2.0: An end -to-end benchmarking framework for compute -in-memory accelerators for on -chip training,.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures DNN+NeuroSim V2.0: An end -to-end benchmarking framework for compute -in-memory accelerators for on -chip training,

Reference 47

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This paper cites Detailed and Flexible Cycle-Accurate Network-on-Chip Simulator,.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures Detailed and Flexible Cycle-Accurate Network-on-Chip Simulator,

Reference 48

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This paper cites https://huggingface.co/docs/peft/en/index,.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures https://huggingface.co/docs/peft/en/index,

Reference 49

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T19:57:26.029242Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation a76e4e69-360e-4a79-af87-0bf741cc1e31 · outbound

This paper cites Cost analysis and cost-driven IP reuse methodology for SoC design based on 2.5D/3D integration,.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures Cost analysis and cost-driven IP reuse methodology for SoC design based on 2.5D/3D integration,

Reference 50

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T19:57:26.021109Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation d393243d-56f4-46d7-bc88-5838ac1e5abf · outbound

This paper cites Temperature - and Cost-Aware Design of 3D Multiprocessor Architectures,.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures Temperature - and Cost-Aware Design of 3D Multiprocessor Architectures,

Reference 51

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T19:57:26.013060Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation cd57d947-d27b-403e-b265-c7afeee073bd · outbound

This paper cites Cost Modeling and Analysis of TSV and Contactless 3D-ICs,.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures Cost Modeling and Analysis of TSV and Contactless 3D-ICs,

Reference 52

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T19:57:26.004279Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation 83d51ef1-df9f-4e9a-9655-3e5db5815628 · outbound

This paper cites Cost and Thermal Analysis of High -Performance 2.5D and 3D Integrated Circuit Design Space,.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures Cost and Thermal Analysis of High -Performance 2.5D and 3D Integrated Circuit Design Space,

Reference 53

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T19:57:25.994960Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation 21335bd2-5190-4a37-b544-8c758fb90143 · outbound

This paper cites NeFT: Negative Feedback Training to Improve Robustness of Compute-In-Memory DNN Accelerators.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures NeFT: Negative Feedback Training to Improve Robustness of Compute-In-Memory DNN Accelerators

Reference 54

Resolution: verified exact; local_arxiv, observed 2026-08-10T19:57:25.737683Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation b518d8ce-3036-4985-bab2-5f1f1efe0b84 · outbound

This paper cites Multi -objective optimization of ReRAM crossbars for robust DNN inferencing under stochastic noise,.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures Multi -objective optimization of ReRAM crossbars for robust DNN inferencing under stochastic noise,

Reference 55

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T19:57:25.986263Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation f7193338-624b-4808-9510-4cd89931fcba · outbound

This paper cites Improving the robustness of analog deep neural networks through a Bayes -optimized noise injection approach,.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures Improving the robustness of analog deep neural networks through a Bayes -optimized noise injection approach,

Reference 56

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T19:57:25.976892Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation 8a3bfc6d-dc2f-482f-91a5-05cc8bd53975 · outbound

This paper cites AccuReD: High Accuracy Training of CNNs on ReRAM/GPU Heterogeneous 3D Architecture,.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures AccuReD: High Accuracy Training of CNNs on ReRAM/GPU Heterogeneous 3D Architecture,

Reference 57

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T19:57:25.969296Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

Observation 348f180a-2033-4567-bd21-16e4ad6c6054 · outbound

This paper cites Newton: A DRAM -maker’s Accelerator -in-Memory (AiM) Architecture for Machine Learning,.

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures Newton: A DRAM -maker’s Accelerator -in-Memory (AiM) Architecture for Machine Learning,

Reference 58

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T19:57:25.960558Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.

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Outbound references

Pith citing papers