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REVIEW 3 major objections 4 minor 44 references

ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits

T0 review · 3 major / 4 minor · reviewed 2026-08-12 · deepseek-v4-flash

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Pith's one-line read The paper builds a simulation framework for SRAM-based analog compute-in-memory inference and claims that even 1 LSB of analog readout noise can seriously damage accuracy on ImageNet-class tasks, while bit-parallel encoding and hybrid or…

desk verdict Open-source SRAM ACiM simulator with solid qualitative noise findings, but the silicon validation is underdetermined. read the letter →

arxiv 2411.11022 v4 pith:HQHYYH2I submitted 2024-11-17 cs.AR

Wenlun Zhang , Shimpei Ando , Yung-Chin Chen , Kentaro Yoshioka This is my paper · ORCID
classification cs.AR
keywords compute-in-memorySRAManaloginferenceaccuracyADCquantizationbit-parallelencodingnoisenoise-awaretraining
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper introduces ASiM, a simulation framework that models SRAM-based analog compute-in-memory inference by decomposing multi-bit MACs into binary cycles and injecting ADC quantization and analog noise on each cycle's column voltage. The central claim is that even 1 LSB of analog readout noise can significantly impair accuracy, and that this sensitivity is much worse for ImageNet and Transformer workloads than for CIFAR-10 CNNs. A second claim is that bit-parallel activation encoding improves energy efficiency with only modest accuracy loss, if ADC precision is raised accordingly. The paper also argues that hybrid analog-digital execution and majority voting on the most significant bit cycles restore accuracy while keeping most of the energy advantage. The evidence includes a silicon correlation where the simulator predicted 91.84% accuracy and the prototype measured 91.70%.

What carries the argument

The central object is the binary-cycle decomposition of the MAC operation, together with bit-parallel encoding that packs several activation bits into one DAC level to cut the number of cycles. In each cycle the ideal column voltage is computed, perturbed by a two-part analog noise model, and rounded by a full-dynamic-range ADC: zero-mean Gaussian random noise for thermal and comparator errors, plus capacitor-mismatch nonlinearity that scales with the number of capacitors. The load-bearing behavior is that DNN weights and activations are bit-sparse in a structured way, so most cycles' signal spans only a small fraction of the ADC range; errors in the most significant bit cycles are then multiplied by large bit-shift weights and produce outliers that expand the quantization scale in later layers. This is why the paper can claim 1 LSB noise is harmful while quantization noise alone is not, and why offloading MSB cycles to digital logic or oversampling them with majority voting helps.

What would settle it

Take a second, independently fabricated SRAM ACiM macro, measure its ADC readout error distribution directly, feed that measured error into ASiM without fitting a 50/50 random-to-nonlinearity split, and compare predicted versus measured end-to-end accuracy for several ADC precisions on ImageNet; if the predicted inflection point shifts or the accuracy gap exceeds the roughly 0.14-point margin seen on the prototype, the model's central claim is falsified.

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Extended reading notes

Core claim

The paper claims that whether an SRAM-based analog compute-in-memory circuit preserves DNN accuracy can be decided in simulation, provided the simulation keeps three effects explicit: ADC rounding over the full dynamic range, bit-parallel activation encoding, and per-cycle analog noise on the column voltage. On that basis it argues that analog readout noise is the dominant accuracy limiter: a noise of 1 LSB at the ADC can seriously degrade accuracy on ImageNet-level tasks, while CNNs on CIFAR-10 tolerate more. Bit-parallel encoding with appropriately raised ADC precision still delivers large energy savings with modest accuracy loss. The silicon-correlation result, an ASiM prediction of 91.84% versus 91.70% measured on the authors' prototype, is offered as evidence that the simulator captures the relevant circuit behavior.

Load-bearing premise

The whole analysis rests on the assumption that every relevant analog imperfection in an SRAM compute-in-memory chip shows up as zero-mean Gaussian scatter on the column voltage plus a capacitor-mismatch bend in the voltage scale, and that any fixed voltage offset can be calibrated away; that model was fitted and checked on a single prototype at one operating point, so its quantitative predictions may not transfer to circuits with correlated, non-Gaussian, or uncalibrated errors.

Editorial extensions

If this is right

  • ImageNet-level SRAM ACiM designs must budget analog readout noise well below 1 LSB, roughly 0.025 to 0.1 LSB rms for 4-bit activation encoding at an 8-bit ADC, or accuracy collapses.
  • Bit-parallel encoding with 4 activation bits can cut energy per classification by up to about four times on CIFAR-10/ResNet-18 while losing under a point of accuracy, and still saves roughly 40% energy on the hardest ViT/ImageNet combination.
  • CNN models on CIFAR-10 can drop ADC precision 1 to 2 bits below the lossless readout level with minor loss, but ViT-B-32 on ImageNet loses about 10% per bit below that level, and on CIFAR-10 it approaches random guessing.
  • Hybrid analog-digital execution can recover near-baseline accuracy under 0.8 LSB rms noise while keeping a large majority of cycles analog, and even for ViT/ImageNet retains over 40% of cycles in the analog domain.
  • Oversampling the six most significant bit cycles seven times with majority voting reaches about 90% accuracy at 0.7 LSB rms noise with a cycle overhead below 40%, reducing the effective noise standard deviation approximately by the square root of the sampling count.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If the 1 LSB sensitivity transfers, SRAM ACiM datasheets should report ADC readout noise in LSB rms; any design that omits this number is underspecified for accuracy.
  • The sparsity mechanism suggests a testable extension: architectures that increase bit-level sparsity through pruning or thresholding would push MAC outputs even lower into the ADC range, making MSB-cycle noise relatively worse unless noise is also lowered.
  • Because the validation split between random noise and nonlinearity was fixed after seeing the measured error, the quantitative noise thresholds should be re-derived from a measured noise breakdown on a second chip before being treated as universal design rules.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 4 minor

Summary. This manuscript presents ASiM, an open-source PyTorch simulation framework for evaluating the inference accuracy of SRAM-based analog compute-in-memory (ACiM) macros. The framework decomposes quantized weights and activations into bit-serial or bit-parallel MAC cycles, models ADC rounding over the full dynamic range, and injects two noise components: zero-mean Gaussian random noise and a capacitor-mismatch nonlinearity. Using ResNet-18 and ViT-B-32 on CIFAR-10 and ImageNet, the authors report that (i) analog noise of about 1 LSB significantly degrades accuracy, especially for complex tasks such as ImageNet and for Transformer models; (ii) bit-parallel encoding yields substantial energy savings with modest quantization-induced loss but increases sensitivity to analog noise; and (iii) hybrid analog-digital execution and majority voting on MSB cycles restore much of the lost accuracy. The noise model is supported by a 30,000-trial ADC error distribution from the authors' CR-CIM chip, and the framework's predicted accuracy (91.84%) is compared with a silicon measurement (91.70%) at one operating point.

Significance. If the reported trends are robust, ASiM fills a practical gap: it is one of the few open-source, SRAM-specific ACiM inference simulators that supports Transformer workloads and bit-parallel encoding, and it offers concrete design guidance (ADC precision at or above boundary precision; analog noise below roughly 0.4 LSBrms for simple tasks and below about 0.5 mV for complex tasks). The bit-decomposition and ADC-rounding derivations in Sections III-B and IV-B are straightforward and appear correct, and the authors are explicit about the assumptions behind their noise abstraction. The MSB-cycle sensitivity analysis and the cross-design comparison in Fig. 15 are useful for architects. The main weakness is that the quantitative thresholds rest on a noise model whose two components are not separately identified by the single-chip validation, and on NAT training intensities chosen per task; the assumed 0.5-LSB value for designs in Fig. 15 also introduces uncertainty into the cross-design comparison.

major comments (3)
  1. [III-B.5, IV-D] The split between random noise and nonlinearity is not identified by the validation. In Section IV-D the measured LSB-rms noise is 'equally divided and allocated into random noise and nonlinearity,' but the measured ADC error distribution in Fig. 12 and the single accuracy match (91.84% vs. 91.70%) are compatible with many other splits, and the two components have different consequences: Section V-B explicitly notes that majority voting does not reduce systematic errors, while random noise is reduced by oversampling. Because Fig. 9, the 1-LSB threshold, and the bit-parallel conclusions are generated with this 50/50 split, their quantitative values are not uniquely supported. Please show the sensitivity of the main accuracy curves to the split ratio (e.g., 0/100, 25/75, 75/25) or validate the model on a second macro or operating point.
  2. [III-D, IV-C] The NAT training-noise intensity is a free parameter that directly affects the reported noise thresholds. Models in Fig. 9 are fine-tuned at a single training noise level (for example, 100% for ResNet-18/CIFAR-10, 60% for ViT/CIFAR-10, and 50% and 40% for ImageNet), selected to keep the baseline accuracy within 2–3% of the digital model. The sharp accuracy cliffs and the 'below 0.5 mV' design rule for complex tasks may therefore be sensitive to the chosen training noise rather than being a property of the ACiM hardware alone. Please provide a sensitivity sweep over training noise intensity (analogous to Fig. 17 but with the training sigma varied) and state whether the recommended thresholds change.
  3. [VI-C, Table III] The cross-design comparison in Fig. 15 assigns a nominal LSB rms of 0.5 to designs that do not report noise (Spar.-Adapt. [13] and Hybrid [42]) and uses that value to position those designs and to support the claim that lower-LSB designs better tolerate aggressive configurations. This assumption can alter the ranking; a design assumed at 0.5 LSB may move substantially on the accuracy-energy plane if its actual noise is 0.2 or 1.0 LSB. Please report the sensitivity of Fig. 15 to this assumed value or replace the assumed values with measured ones.
minor comments (4)
  1. [II-C, Eqs. (2)-(3)] As typeset, SQNR = σ_y^2/σ_yi^2 + σ_y^2/σ_yo^2 is a sum of two ratios rather than the standard signal-to-noise form with noise variances in a common denominator; please check whether this is a typo and, if not, explain the intended definition.
  2. [III-B.5] The nonlinearity model is described verbally as being 'scaled by √N' and is illustrated in Fig. 19, but the exact transformation applied to the CBL voltage is not given as an equation; please specify it explicitly so that the implementation is fully reproducible.
  3. [Algorithm 1] The noise function fN(σ) is called in line 8 of Algorithm 1, but its definition and the units of σ are not given in the algorithm; please refer explicitly to the parameters and equations in Section III-B.5.
  4. [Figs. 6-7] The shmoo tables list four accuracy values per row with header information split across two lines (e.g., 'CIFAR-10 (92.08%) ImageNet (65.49%)' and 'ResNet-18 ViT-B-32'); please reformat the tables so each column has a single unambiguous header mapping to model and dataset.

Circularity Check

0 steps flagged · score 1.0 of 10

No significant circularity: ASiM's accuracy findings are forward simulation results; the single silicon correlation is in-sample and underdetermined by the 50/50 noise split, but no prediction reduces to its inputs by construction.

full rationale

ASiM's core derivation is a forward bit-wise simulation: given weight/activation bit tensors, it computes ideal CBL voltages (Algorithm 1), injects Gaussian noise and nonlinearity with user-specified intensities (Section III-B.5), rounds through a full-range ADC model (Eq. 5), and accumulates with bit shifts. The central findings—ADC-precision sensitivity (Figs. 6-7), the 1 LSB analog-noise cliff (Fig. 9), MSB-cycle error amplification (Fig. 11), and the benefits of HCiM/majority voting (Figs. 13-14)—are consequences of these forward operations on model distributions, not restatements of the inputs. The only silicon correlation (Section IV-D) uses the authors' own CR-CIM chip [30] and splits the measured total LSB-rms noise 50/50 between random noise and nonlinearity; this single-point match (91.84% vs 91.70%) is an in-sample consistency check rather than an out-of-sample prediction, and the unconstrained split underdetermines which noise component produces the error. That is an evidence-strength limitation, not a circular reduction: the measured ADC error distribution in Fig. 12 independently supports the Gaussian shape, and no fitted parameter is renamed as a prediction. Self-citations to the authors' prior CIM work [25], [30], [35] are used for architecture parameters, the noise-injection idea, and sparsity proportionality; the sparsity claim is re-derived in the Appendix (Eqs. 7-8), and the noise model is checked against measured silicon. The authors also explicitly acknowledge that majority voting does not mitigate systematic errors (Section V-B) and that static offset is omitted as calibratable (Section III-B.5), further indicating the limits are stated rather than concealed. Overall, the derivation does not reduce to its inputs by construction.

Assumptions & free parameters 3 free parameters · 5 assumptions · 0 invented entities

No new physical entities are introduced. The central claims rest on the Gaussian-plus-nonlinearity noise model, the full-range ADC model, and hand-chosen training/validation parameters; silicon validation is limited to the authors' own chip.

free parameters (3)
  • Noise split ratio (random vs nonlinearity) = 0.5/0.5
    In silicon validation, the measured aggregate LSB rms noise was split equally into random noise and nonlinearity; this split is a post hoc choice that affects simulated accuracy predictions and is not independently measured.
  • NAT training noise intensities = 100% (CIFAR-10/ResNet-18), 50% (ImageNet/ResNet-18), 60% (CIFAR-10/ViT-B-32), 40% (ImageNet/ViT-B-32)
    Selected by hand to trade off baseline accuracy against noise robustness; these choices determine the baseline accuracies (92.08, 65.49, 95.26, 68.17) used throughout the experiments.
  • LSB rms for designs without reported noise = 0.5 LSB
    In the Fig. 15 comparison of SOTA designs, a nominal 0.5 LSB rms is assumed for designs that do not report noise; this can influence the relative accuracy ranking.
assumptions (5)
  • standard math 2's complement bit decomposition of MAC (Eq. 1) is exact given integer weights and activations.
    Used implicitly throughout Algorithm 1 and the framework.
  • domain assumption The CBL voltage is proportional to the count of bit-wise products and is read out by an ADC with full-range clamping and round-to-nearest (Eq. 5).
    This is the core ADC model; alternatives (adaptive range, min-max) are argued to be optimistic. Validated against the authors' CR-CIM chip.
  • domain assumption Cumulative analog noise can be modeled as zero-mean Gaussian on the CBL voltage plus a capacitor-mismatch nonlinearity scaled by sqrt(N).
    Adopted to abstract kT/C, comparator errors, and mismatch; validated by ADC error distribution on one chip, but not for all SRAM ACiM designs.
  • standard math Bit-level sparsity of weights and activations are independent (P(w=1 and x=1) = P(w=1)P(x=1)).
    Used in appendix Eq. 7-8 to explain the narrow MAC span; may not hold exactly but only illustrative.
  • ad hoc to paper Per-tensor uniform quantization is representative for evaluating ACiM accuracy, including for ViT.
    Used for all experiments; known to be suboptimal for Transformers and may affect the ViT sensitivity results.

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Cite this review

Pith. "Pith review of ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits." pith.science (2026). https://pith.science/paper/HQHYYH2I

@misc{pith2026241111022,
  author       = {Pith},
  title        = {Pith review of: ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/HQHYYH2I}},
  note         = {Machine review of arXiv:2411.11022}
}
read the original abstract

SRAM-based Analog Compute-in-Memory (ACiM) demonstrates promising energy efficiency for deep neural network (DNN) processing. Nevertheless, efforts to optimize efficiency frequently compromise accuracy, and this trade-off remains insufficiently studied due to the difficulty of performing full-system validation. Specifically, existing simulation tools rarely target SRAM-based ACiM and exhibit inconsistent accuracy predictions, highlighting the need for a standardized, SRAM CiM circuit-aware evaluation methodology. This paper presents ASiM, a simulation framework for evaluating inference accuracy in SRAM-based ACiM systems. ASiM captures critical effects in SRAM based analog compute in memory systems, such as ADC quantization, bit parallel encoding, and analog noise, which must be modeled with high fidelity due to their distinct behavior in charge domain architectures compared to other memory technologies. ASiM supports a wide range of modern DNN workloads, including CNN and Transformer-based models such as ViT, and scales to large-scale tasks like ImageNet classification. Our results indicate that bit-parallel encoding can improve energy efficiency with only modest accuracy degradation; however, even 1 LSB of analog noise can significantly impair inference performance, particularly in complex tasks such as ImageNet. To address this, we explore hybrid analog-digital execution and majority voting schemes, both of which enhance robustness without negating energy savings. ASiM bridges the gap between hardware design and inference performance, offering actionable insights for energy-efficient, high-accuracy ACiM deployment.

Figures

Figures reproduced from arXiv: 2411.11022 by the authors.

Figure 1
Figure 1. Fundamental architecture and MAC operation of ACiM. (a) Bit-serial [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 2
Figure 2. ASiM framework overview: ASiM is a plug-and-play simulation framework tailored for charge-domain ACiM inference. Users can seamlessly replace [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 3
Figure 3. Noise-Aware Training: accuracy of 8b/8b baseline models across dif [PITH_FULL_IMAGE:figures/full_fig_p006_3.png] view at source ↗
Figures from the paper (15 more)
Figure 4
Figure 4. Figure 4: Quantized DNN model input distribution analysis. (a) Data distribution [PITH_FULL_IMAGE:figures/full_fig_p007_4.png]
Figure 5
Figure 5. Figure 5: Distribution of MAC outputs in the convolutional layer of a 6b/6b CNN for each bit-serial cycle, using an ACiM macro with row parallelism of 256 [PITH_FULL_IMAGE:figures/full_fig_p008_5.png]
Figure 6
Figure 6. Figure 6: Shmoo plot of inference accuracy under varying ADC precision for a [PITH_FULL_IMAGE:figures/full_fig_p008_6.png]
Figure 7
Figure 7. Figure 7: Shmoo plot of inference accuracy under varying ADC precision for a bit-parallel ACiM macro with a row-parallelism of 256, evaluated using an [PITH_FULL_IMAGE:figures/full_fig_p009_7.png]
Figure 8
Figure 8. Figure 8: Energy cost and corresponding inference accuracy for bit-serial and [PITH_FULL_IMAGE:figures/full_fig_p009_8.png]
Figure 9
Figure 9. Figure 9: Shmoo plot of inference accuracy across different noise intensities for an ACiM macro with a row-parallelism of 256 using an 8-bit ADC, evaluated [PITH_FULL_IMAGE:figures/full_fig_p010_9.png]
Figure 10
Figure 10. Figure 10: Accuracy degradation under different noise intensities for bit [PITH_FULL_IMAGE:figures/full_fig_p010_10.png]
Figure 11
Figure 11. Figure 11: Real-world example of bit-serial MAC in 3b/3b ResNet-18 on [PITH_FULL_IMAGE:figures/full_fig_p010_11.png]
Figure 13
Figure 13. Figure 13: Digital-Analog HCiM for DNN inference accuracy improvement. (a) [PITH_FULL_IMAGE:figures/full_fig_p011_13.png]
Figure 14
Figure 14. Figure 14: Oversampling MSB cycles with majority voting to improve inference [PITH_FULL_IMAGE:figures/full_fig_p012_14.png]
Figure 15
Figure 15. Figure 15: Comparison of state-of-the-art CiM designs analyzed using ASiM. [PITH_FULL_IMAGE:figures/full_fig_p013_15.png]
Figure 16
Figure 16. Figure 16: Distribution of MAC outputs in the Query Projection of a 6b/6b ViT-B-32 for each bit-serial cycle, using an ACiM macro with row parallelism of [PITH_FULL_IMAGE:figures/full_fig_p016_16.png]
Figure 18
Figure 18. Figure 18: Shmoo plot of inference accuracy across different random noise [PITH_FULL_IMAGE:figures/full_fig_p016_18.png]
Figure 17
Figure 17. Figure 17: Inference accuracy of 8b/8b ResNet-18 and ViT-B/32 models, with [PITH_FULL_IMAGE:figures/full_fig_p016_17.png]
Figure 19
Figure 19. Figure 19: Linearity plots of a 4-bit ADC under different noise models: (a) Random noise. (b) Nonlinearity-induced distortion. (c) Random noise with majority [PITH_FULL_IMAGE:figures/full_fig_p017_19.png]

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Pith tools

Reviewed August 12, 2026 · model on record in the stance chip above.