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QCDOC: A 10-teraflops scale computer for lattice QCD

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arxiv hep-lat/0011004 v1 pith:HZV5HJ5T submitted 2000-11-01 hep-lat

D. Chen , N. H. Christ , C. Cristian , Z. Dong , A. Gara , K. Garg , B. Joo , C. Kim
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L. Levkova X. Liao R. D. Mawhinney S. Ohta T. Wettig
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classification hep-lat
keywords latticeqcdocadditionalarchitecturecalculationschipcircuitcircuitry
verification ladder T0 review T1 audit T2 compute T3 formal
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The architecture of a new class of computers, optimized for lattice QCD calculations, is described. An individual node is based on a single integrated circuit containing a PowerPC 32-bit integer processor with a 1 Gflops 64-bit IEEE floating point unit, 4 Mbyte of memory, 8 Gbit/sec nearest-neighbor communications and additional control and diagnostic circuitry. The machine's name, QCDOC, derives from ``QCD On a Chip''.

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