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arxiv: 2606.22482 · v1 · pith:J2V2UA3Qnew · submitted 2026-06-21 · 💻 cs.AR

NeutronSparse: Coordinating Heterogeneous Engines for Sparse Matrix Multiplication on NPUs

Xin Ai , Zeyu Ling , Hao Yuan , Qiange Wang , Yanfeng Zhang , Yutao Peng , Ge Yu This is my paper

Pith reviewed 2026-06-26 09:51 UTC · model grok-4.3

classification 💻 cs.AR
keywords sparse matrix multiplicationSpMMNPUsheterogeneous enginestile orchestrationAscend 910Bperformance optimizationdata coordination
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The pith

NeutronSparse accelerates sparse matrix multiplication on NPUs by coordinating heterogeneous engines and orchestrating data tiles.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper establishes that the main limit on SpMM performance for NPUs is inefficient coordination between heterogeneous compute units inside a tile-based execution model. NeutronSparse fixes this with adaptive workload partitioning that keeps units busy and with data-tile reuse that cuts redundant memory traffic. On the Ascend 910B these changes produce 1.26x-7.78x gains over prior NPU code and 1.03x-3.07x gains over leading GPU sparse libraries. A reader would care because NPUs are already deployed for efficiency in data centers, and sparse linear algebra is central to graph and machine-learning workloads. The result shows that careful scheduling of existing hardware units can close the gap with GPUs without new silicon.

Core claim

NeutronSparse is a coordination-first SpMM framework that combines sparsity-aware coordination of heterogeneous engines, which adaptively partitions and balances workloads between compute units, with locality-aware tile orchestrating, which reorganizes and reuses data tiles. On Ascend 910B the framework reaches 1.26x-7.78x speedup over NPU baselines and 1.03x-3.07x speedup over cuSPARSE on A100, while the vendor MindSpore implementation only attains 36.3 percent of the GPU library performance.

What carries the argument

Sparsity-aware coordination of heterogeneous engines together with locality-aware tile orchestrating, which together balance workloads and reduce redundant data movement under the tile-based model.

If this is right

  • Heterogeneous NPU units can reach high utilization on irregular sparse data when workloads are partitioned adaptively.
  • Redundant computation and memory traffic in tile-based SpMM shrink when data tiles are reused across engines.
  • NPUs can match or exceed current GPU sparse libraries for this workload on Ascend 910B hardware.
  • The untapped potential of NPUs for sparse computation becomes usable once the coordination gap is closed.
  • Data-management challenges that currently limit SpMM on NPUs are addressed by explicit engine balancing and tile reuse.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same coordination approach could be tested on other NPU designs that also expose multiple engine types.
  • Extending the tile-orchestration logic to additional sparse kernels such as SpMV would be a direct next measurement.
  • Measuring energy per operation alongside throughput would show whether the coordination gains preserve the efficiency advantage of NPUs.
  • Porting the scheduling logic into a higher-level framework would let application writers benefit without rewriting kernels.

Load-bearing premise

The key performance bottleneck for SpMM on NPUs lies in the lack of efficient coordination across heterogeneous compute units under the tile-based execution model.

What would settle it

A side-by-side timing of the same SpMM kernels on Ascend 910B with the coordination and tile-orchestration passes turned off versus turned on, to check whether the reported speedups appear.

Figures

Figures reproduced from arXiv: 2606.22482 by Ge Yu, Hao Yuan, Qiange Wang, Xin Ai, Yanfeng Zhang, Yutao Peng, Zeyu Ling.

Figure 1
Figure 1. Figure 1: Comparison of SpMM performance between the Ascend 910B and Nvidia A100. [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Resource allocation in NPU AI Cores and GPU SMs. [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Overview of the Nvidia GPU architecture. [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figure 5
Figure 5. Figure 5: Effective overlap between heterogeneous compute engines on NPU vs. GPU. [PITH_FULL_IMAGE:figures/full_fig_p005_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: AIC/AIV utilization timeline on ogbn-arxiv. Limitation of Existing NPU Baselines. We further analyze how prior Ascend SpMM imple￾mentations utilize heterogeneous engines within a fixed execution window on ogbn-arxiv. We profile the execution timeline of AIV and AIC and report their utilization patterns. As shown in [PITH_FULL_IMAGE:figures/full_fig_p006_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Workflow of NeutronSparse. tile size 𝑡 ∈ {4, 16, 32, 64, 128} and conceptually tile each matrix; following a tile-centric execution abstraction, a tile is marked active if it contains at least one nonzero, and the kernel processes active tiles as whole 𝑡×𝑡 units. We then report the fraction of zeros inside all active tiles as a proxy for tile-induced redundant work. As summarized in [PITH_FULL_IMAGE:figur… view at source ↗
Figure 8
Figure 8. Figure 8: SpMM execution on heterogeneous AIC and AIV engines: (a) Sparse, vector-oriented execution on AIV, (b) Dense, matrix-oriented execution on AIC. hierarchy (Section 6.2) by staging frequently accessed dense 𝐵 rows for cross-core reuse while choosing per-core tile shapes that saturate private buffers and favor efficient transfers. Finally, AIV and AIC kernels (Section 5.1) consume the prepared tile streams co… view at source ↗
Figure 9
Figure 9. Figure 9: Heterogeneous workload partitioning. The sparse matrix is first partitioned by rows into a dense part [PITH_FULL_IMAGE:figures/full_fig_p010_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: Load migration under runtime load imbalance. [PITH_FULL_IMAGE:figures/full_fig_p011_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: Global Reordering. where 𝑅 ′ AIC = 𝑅 \ 𝑅 ′ AIV, and 𝑀(𝑅 ′ AIC) denotes the number of rows in the AIC-assigned workload. This condition aligns the workloads according to the throughput capabilities of the two engines and corresponds to the sparsity threshold 𝛼. 6 LOCALITY-AWARE TILE ORCHESTRATING On NPUs, SpMM is fundamentally governed by the tile as the minimum unit of computation and data movement. While… view at source ↗
Figure 12
Figure 12. Figure 12: Local Reordering. block-like regions in the reordered matrix. Such a coarse permutation captures the major structural correlations needed by the subsequent local reordering, while keeping preprocessing overhead low and avoiding unnecessary fragmentation for tile-oriented execution. Local Reordering. After global clustering, residual sparsity still exists inside each cluster. Rather than continuing expensi… view at source ↗
Figure 13
Figure 13. Figure 13: Vector tiles merging. Row Window List 0 1 2 3 4 5 6 7 2 3 6 0 7 0 1 2 3 4 5 6 7 2 3 6 0 7 0 1 2 3 4 5 6 7 2 3 6 0 7 Window Migration Balanced List Extra Write = 1 Extra Write = 1 Extra Write = 1 [PITH_FULL_IMAGE:figures/full_fig_p015_13.png] view at source ↗
Figure 15
Figure 15. Figure 15: SpMM performance on Ascend 910B and Nvidia A100 [PITH_FULL_IMAGE:figures/full_fig_p017_15.png] view at source ↗
Figure 16
Figure 16. Figure 16: Performance gain of AIV-AIC Coordination. [PITH_FULL_IMAGE:figures/full_fig_p018_16.png] view at source ↗
Figure 17
Figure 17. Figure 17: Dynamic balance AIV-AIC workload. Epoch Time AIV/AIC Workload Ratio Epoch Number (b) Extreme AIV Workload Time(ms) Workload Ratio 0 50 100 200 300 600 0.0 2.0 4.0 6.0 8.0 +∞ 1 2 3 4 5 6 7 8 9 10 Epoch Time AIV/AIC Workload Ratio Epoch Number (a) Extreme AIC Workload Time(ms) Workload Ratio 0 50 100 200 300 400 0.0 0.4 0.8 1.2 1.6 2.0 1 2 3 4 5 6 7 8 9 10 [PITH_FULL_IMAGE:figures/full_fig_p018_17.png] view at source ↗
Figure 18
Figure 18. Figure 18: Convergence of online workload migration under extreme initial-skew cases. Online Workload Migration [PITH_FULL_IMAGE:figures/full_fig_p018_18.png] view at source ↗
Figure 19
Figure 19. Figure 19: Sensitivity of SpMM performance to the initial sparsity threshold. Dataset Baseline Baseline+Reorder Baseline+Reorder+Tile Reuse SpeedUp 0 1 2 3 4 5 6 CR WR DA OL OA PA MP M15 ND HG F1 FA MG ML AU M17 RD AP M18 M19 [PITH_FULL_IMAGE:figures/full_fig_p019_19.png] view at source ↗
Figure 20
Figure 20. Figure 20: Performance gain of locality-aware tile scheduling. [PITH_FULL_IMAGE:figures/full_fig_p019_20.png] view at source ↗
Figure 21
Figure 21. Figure 21: Density improvement of global-local reordering. "GR": global reordering, "LR": local reordering. [PITH_FULL_IMAGE:figures/full_fig_p020_21.png] view at source ↗
Figure 22
Figure 22. Figure 22: Performance with varying tile sizes. and further add hierarchical tile reusing (Baseline+Reorder+Tile Reuse), reporting speedups normal￾ized to the baseline. Overall, Baseline+Reorder achieves an average speedup of 2.17× by clustering correlated rows/columns into communities and forming denser row-window tiles, which reduces redundant work on sparsely populated tiles. On top of that, Tile Reuse provides a… view at source ↗
Figure 23
Figure 23. Figure 23: Scaling performance when varying matrix sizes. [PITH_FULL_IMAGE:figures/full_fig_p021_23.png] view at source ↗
Figure 24
Figure 24. Figure 24: Power draw (in watts) sampled every 100ms over a 10-second training window (Dataset: reddit). [PITH_FULL_IMAGE:figures/full_fig_p023_24.png] view at source ↗
Figure 25
Figure 25. Figure 25: Cost-normalized SpMM throughput using hourly cloud rental prices. [PITH_FULL_IMAGE:figures/full_fig_p023_25.png] view at source ↗
Figure 26
Figure 26. Figure 26: TFLOPS-normalized SpMM performance comparison on Ascend 910B and NVIDIA H100. baselines in performance per dollar. On average, NeutronSparse achieves 2.47×, 1.49×, and 1.43× higher cost efficiency than cuSPARSE, DTC-SpMM, and HC-SpMM, respectively. These results indicate that the advantage mainly comes from improved execution efficiency rather than pricing differences, suggesting that NPU-aware optimizati… view at source ↗
Figure 27
Figure 27. Figure 27: SpMM performance on Cambricon MLU across all 20 datasets. absolute compute capability of H100, NeutronSparse still delivers competitive sparse-computation efficiency. 8.10 Portability to Another NPU Backend To further evaluate cross-device portability, we port NeutronSparse to Cambricon MLU and compare it against the SpMM implementation provided by PyTorch on the same platform. The port preserves the core… view at source ↗
read the original abstract

Sparse matrix-matrix multiplication (SpMM) is a fundamental data operation for large-scale sparse data processing. With NPUs increasingly deployed in data centers for their performance and energy efficiency, accelerating SpMM on these platforms is a natural choice. However, high-performance SpMM on NPUs poses a data management challenge, as irregular sparsity demands efficient data organization and scheduling. On Ascend 910B, the official MindSpore implementation achieves only 36.3% of the performance of GPU-based sparse libraries such as cuSPARSE on NVIDIA A100. To this end, we conduct an in-depth architectural analysis of SpMM execution on NPUs versus GPU and identify that the key performance bottleneck for SpMM on NPUs lies in the lack of efficient coordination across heterogeneous compute units under tile-based execution model. Therefore, we propose NeutronSparse, a coordination-first SpMM framework for NPUs. NeutronSparse integrates two key techniques: (i) Sparsity-aware coordination of heterogeneous engines, which adaptively partitions and balances workloads between heterogeneous compute units to keep them busy, and (ii) Locality-aware tile orchestrating, which reorganizes and reuses data tiles to reduce redundant computation and memory movement overhead. Evaluations on Ascend 910B show that NeutronSparse achieves 1.26x-7.78x speedup over NPU baselines and 1.03x-3.07x speedup over leading GPU libraries on NVIDIA A100, revealing untapped potential of NPUs for sparse computation.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

0 major / 1 minor

Summary. The paper proposes NeutronSparse, a SpMM framework for NPUs that identifies the bottleneck in coordinating heterogeneous compute units under tile-based execution. It introduces two techniques: sparsity-aware coordination of heterogeneous engines and locality-aware tile orchestrating. The work reports speedups of 1.26x-7.78x over NPU baselines and 1.03x-3.07x over GPU libraries.

Significance. If the results hold, this is a significant contribution to the field as it shows the potential of NPUs for sparse computation through better coordination, which could impact the design of future NPU software for data center workloads. The architectural analysis and proposed techniques provide a foundation for optimizing irregular workloads on heterogeneous accelerators.

minor comments (1)
  1. [Abstract] The abstract states performance numbers but supplies no methodology, dataset details, error bars, or verification steps. While the full manuscript likely contains these details in the evaluation section, the abstract would benefit from a high-level mention to allow readers to assess the claims at a glance.

Simulated Author's Rebuttal

0 responses · 0 unresolved

We thank the referee for the positive evaluation and recommendation for minor revision. The report identifies the core contribution correctly. Since no specific major comments were raised, we have no points to address point-by-point at this stage. We will incorporate any minor suggestions during revision.

Circularity Check

0 steps flagged

No significant circularity

full rationale

The paper is an empirical systems contribution that identifies a performance bottleneck via architectural analysis of NPUs versus GPUs, then evaluates two proposed coordination techniques through direct hardware measurements on Ascend 910B. No equations, fitted parameters, self-citation chains, or definitional reductions appear in the provided text. The speedup claims follow from experimental results rather than any input-by-construction equivalence.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

Abstract-only review supplies no identifiable free parameters, axioms, or invented entities; the central claim rests on an unverified architectural analysis whose details are not provided.

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Reference graph

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