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arxiv: 2606.20414 · v2 · pith:MF3BNFA3new · submitted 2026-06-18 · 💻 cs.AR

ExSpike: A General Full-Event Neuromorphic Architecture for Exploiting Irregular Sparsity with Event Compression

Yuehai Chen , Farhad Merchant This is my paper

Pith reviewed 2026-06-26 15:17 UTC · model grok-4.3

classification 💻 cs.AR
keywords spiking neural networksfull-event architectureevent compressionneuromorphic hardwareFPGA acceleratorenergy efficiencyirregular sparsitydataflow optimization
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The pith

ExSpike enables pure event-driven execution across all layers of spiking neural networks by optimizing dataflow and compressing adjacent spikes, delivering up to 10 times higher PE-normalized energy efficiency than prior FPGA accelerators.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper aims to show that irregular sparsity in spiking neural networks can be translated into real energy and performance gains through a complete full-event architecture rather than partial event handling. It introduces dataflow changes that keep every layer input as spikes, adds an attention core for spike-driven operations, and applies adjacent-position event compression to cut redundant work. A reader would care because SNNs have long promised efficiency from sparsity but hardware has struggled to capture it without falling back to dense computation or losing accuracy. If the approach holds, neuromorphic designs could move from research prototypes to practical accelerators for tasks like image classification and segmentation.

Core claim

ExSpike is a general full-event neuromorphic architecture that supports pure event-driven dataflow through layer-input optimizations, includes an Attention Core for spike-driven self-attention, and applies adjacent-position event compression to reduce redundant accumulations across spatially adjacent spike sequences; when implemented on AMD Xilinx Virtex-7 FPGA it reaches 479.15 GOPS, 281.85 GOPS/W, and 0.80 GOPS/W/PE while preserving competitive accuracy on classification and segmentation workloads and outperforming the prior FireFly-T design by up to 10 times in PE-normalized energy efficiency.

What carries the argument

The ExSpike full-event architecture, which combines dataflow optimizations to enforce spike-based layer inputs with adjacent-position event compression to eliminate redundant accumulations.

If this is right

  • SNN accelerators can maintain full spike-driven execution end-to-end without reverting to dense operations at any layer.
  • Adjacent-position event compression reduces accumulations enough to raise overall throughput and efficiency on FPGA hardware.
  • The architecture supports both classification and segmentation tasks while achieving up to 10 times better PE-normalized energy efficiency than FireFly-T.
  • An Attention Core can be integrated into the event-driven flow to handle spike-driven self-attention without breaking sparsity.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same compression and dataflow ideas could be tested on ASIC targets to see whether the efficiency gains scale beyond FPGA resources.
  • If the spike-based input constraint holds for larger or recurrent SNNs, the design might reduce the need for hybrid dense-sparse hardware blocks.
  • Applying the adjacent-position compression outside SNNs to other sparse temporal data streams could be checked for similar accumulation savings.

Load-bearing premise

The dataflow optimizations can keep every layer input spike-based with negligible overhead or accuracy loss on the evaluated SNN models and workloads.

What would settle it

Running the same SNN models on ExSpike after removing the dataflow optimizations and observing either a shift away from spike-based inputs, a measurable accuracy drop, or energy efficiency falling below the reported 0.80 GOPS/W/PE would falsify the central performance claim.

Figures

Figures reproduced from arXiv: 2606.20414 by Farhad Merchant, Yuehai Chen.

Figure 1
Figure 1. Figure 1: The computation model of different convolutions. [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Layer-wise latency and sparsity analysis of VGG11 on CIFAR-10 under direct-coded SNN inference. Static CIFAR￾10 images are encoded by the first layer into spike events. spike sparsity. EConv outperforms TConv in every layer, achieving up to 97% latency reduction at Conv-7 and 88% reduction on average. The results also show that higher input sparsity leads to larger speedups. For example, when only 10% of s… view at source ↗
Figure 5
Figure 5. Figure 5: Implementation of adjacent-position event compression. [PITH_FULL_IMAGE:figures/full_fig_p004_5.png] view at source ↗
Figure 3
Figure 3. Figure 3: The overall architecture of ExSpike. 0 1 0 0 1 ... 0 1 0 1 0 0 1 0 ... 1 0 0 0 0 0 0 1 ... 0 1 0 1 0 0 0 0 ... 0 0 0 ... 0 0 0 0 0 ... 0 0 1 ... Spike SRAM 1 REG AND 00...0001 00...0010 00...0100 00...1000 ··· 10...0000 one-hot addr 0 1 2 3 ··· x Fast Event Filter NOT NOT AND 0 4 A ··· E R FIFO ❶ ❷ ❸ EPE Core ... ... Weight SRAM W0,0 W0,1 W0,2 ... W0,31 W1,0 W1,1 W1,2 ... W1,31 W2,0 W2,1 W2,2 ... W2,31 W3,… view at source ↗
Figure 4
Figure 4. Figure 4: Hardware implementation of event-driven convolution. [PITH_FULL_IMAGE:figures/full_fig_p004_4.png] view at source ↗
Figure 6
Figure 6. Figure 6: Implementation of the Attention Core. The main overhead of APEC lies in the storage and reuse of overlap partial sums, which can be approximated as 𝑀ov ≈ 𝐶𝑜 𝑘 2𝑤acc, (4) where 𝑤acc denotes the bitwidth of the partial sum. Therefore, although a larger group provides a higher theoretical reuse factor, the overall gain of APEC does not necessarily in￾crease monotonically with group size because the higher-ord… view at source ↗
Figure 7
Figure 7. Figure 7: Performance analysis under different APEC group sizes. (a)–(d) show the block-wise throughput speedup over the baseline [PITH_FULL_IMAGE:figures/full_fig_p006_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Latency breakdown for SpikingFormer-2-512 under [PITH_FULL_IMAGE:figures/full_fig_p006_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: Performance comparison with Intel(R) Xeon 8470Q [PITH_FULL_IMAGE:figures/full_fig_p008_9.png] view at source ↗
read the original abstract

Spiking neural networks (SNNs) promise energy-efficient computing due to their sparse spatio-temporal activity. However, effectively translating such irregular sparsity into practical performance and energy gains remains challenging, as full-event computing architectures are still underexplored. This paper proposes ExSpike, a general full-event neuromorphic architecture that fully exploits irregular sparsity in SNNs. To realize pure event-driven execution, we first propose a set of dataflow optimizations to ensure that the inputs to each SNN layer remain spike-based, thereby enabling full-event execution throughout the network. We then design a hardware-efficient full-event architecture, named ExSpike, which supports the optimized pure event-driven dataflow and an additional Attention Core for spike-driven self-attention. To further improve computing efficiency, we introduce adjacent-position event compression to reduce redundant accumulations across spatially adjacent spike sequences. ExSpike is implemented on an AMD Xilinx Virtex-7 FPGA and evaluated on both classification and segmentation workloads. Experimental results show that ExSpike achieves high normalized energy efficiency across diverse SNN models while maintaining competitive accuracy, delivering up to 479.15 GOPS, 281.85 GOPS/W, and 0.80 GOPS/W/PE. In particular, ExSpike achieves up to 10$\times$ higher PE-normalized energy efficiency than the SOTA FPGA-based SNN accelerator (FireFly-T). The code for ExSpike is available at https://github.com/xiaoyuehai/ExSpike.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The manuscript presents ExSpike, a full-event neuromorphic architecture for SNNs that employs dataflow optimizations to maintain spike-based inputs across layers and adjacent-position event compression to reduce redundant accumulations. It includes an Attention Core for spike-driven self-attention, is implemented on AMD Xilinx Virtex-7 FPGA, and is evaluated on classification and segmentation workloads. The paper reports peak metrics of 479.15 GOPS, 281.85 GOPS/W, and 0.80 GOPS/W/PE, claiming up to 10× higher PE-normalized energy efficiency than the SOTA FPGA accelerator FireFly-T while preserving competitive accuracy; the implementation code is released openly.

Significance. If the experimental claims are substantiated with adequate controls, the work offers a concrete hardware realization of pure event-driven execution for irregular SNN sparsity, extending prior accelerators by supporting attention mechanisms within the same dataflow. The open-source code release is a clear strength that supports reproducibility and further research in neuromorphic FPGA design.

major comments (2)
  1. [Evaluation] Evaluation section: The central 10× PE-normalized efficiency claim (0.80 GOPS/W/PE vs. FireFly-T) and the assertion that dataflow optimizations 'ensure that the inputs to each SNN layer remain spike-based' with negligible overhead require per-layer spike-rate tables, ablation results on accuracy impact, and overhead measurements for the evaluated models; these data are absent, leaving the pure full-event execution assumption unverified and load-bearing for the reported 281.85 GOPS/W figure.
  2. [Experimental Results] Experimental setup: Workload selection criteria, precise baseline configurations (e.g., whether FireFly-T was re-implemented on the identical Virtex-7 device with matching SNN topologies and bit-widths), and error bars or run-to-run variation for the GOPS/W and GOPS/W/PE numbers are not reported, undermining confidence in the cross-accelerator comparison.
minor comments (2)
  1. [Figures/Tables] Figure captions and tables should explicitly state the SNN models, input spike rates, and layer counts used for each efficiency bar to allow direct comparison.
  2. [Architecture] Clarify in the architecture description whether the Attention Core operates fully event-driven or requires any rate-coded preprocessing.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive comments. We address each major comment below and will revise the manuscript accordingly where appropriate.

read point-by-point responses

  1. Referee: [Evaluation] Evaluation section: The central 10× PE-normalized efficiency claim (0.80 GOPS/W/PE vs. FireFly-T) and the assertion that dataflow optimizations 'ensure that the inputs to each SNN layer remain spike-based' with negligible overhead require per-layer spike-rate tables, ablation results on accuracy impact, and overhead measurements for the evaluated models; these data are absent, leaving the pure full-event execution assumption unverified and load-bearing for the reported 281.85 GOPS/W figure.

    Authors: We agree that providing per-layer spike-rate tables, ablation studies on accuracy, and overhead measurements would strengthen the verification of the full-event execution. In the revised version, we will add these details for the evaluated models to substantiate the claims of negligible overhead and pure spike-based inputs across layers. This will support the reported efficiency figures. revision: yes

  2. Referee: [Experimental Results] Experimental setup: Workload selection criteria, precise baseline configurations (e.g., whether FireFly-T was re-implemented on the identical Virtex-7 device with matching SNN topologies and bit-widths), and error bars or run-to-run variation for the GOPS/W and GOPS/W/PE numbers are not reported, undermining confidence in the cross-accelerator comparison.

    Authors: The workloads were selected as representative classification and segmentation tasks from the SNN literature to demonstrate generality. For the baseline, FireFly-T results are cited from the original paper since its source code is not publicly available for re-implementation on the Virtex-7 with exact matching configurations; we will explicitly state this in the revision. The FPGA design is deterministic, so error bars are not applicable, but we will report any measured variations if available. We will also detail the workload selection criteria. revision: partial

Circularity Check

0 steps flagged

No circularity; claims rest on FPGA measurements and implementation

full rationale

The paper describes a hardware architecture (ExSpike) with dataflow optimizations and reports measured results (GOPS, GOPS/W, comparisons to FireFly-T) from Virtex-7 FPGA implementation on classification/segmentation workloads. No equations, fitted parameters, or first-principles derivations are present that could reduce to inputs by construction. Efficiency numbers derive from physical execution traces rather than any self-referential loop. Self-citation is absent from the provided text, and the open-source code link further decouples claims from internal definitions.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

Engineering hardware paper with no mathematical axioms, free parameters, or invented physical entities; design decisions are implementation choices rather than theoretical primitives.

pith-pipeline@v0.9.1-grok · 5801 in / 1096 out tokens · 28128 ms · 2026-06-26T15:17:14.357476+00:00 · methodology

discussion (0)

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Reference graph

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