MCMComm: Hardware-Software Co-Optimization for End-to-End Communication in Multi-Chip-Modules

Ritik Raj; Shengjie Lin; Tushar Krishna; William Won

REVIEW 5 major objections 5 minor 82 references

MCMComm: Hardware-Software Co-Optimization for End-to-End Communication in Multi-Chip-Modules

T0 review · 5 major / 5 minor · reviewed 2026-08-16 · deepseek-v4-flash

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Pith's one-line read For chiplet-based AI accelerators, this paper argues that end-to-end communication should be modeled and optimized jointly across hardware and software, and reports up to 2.7x energy-delay improvement over uniform layer-sequential…

desk verdict MCMComm is a well-structured but unvalidated analytical framework whose headline speedups are likely inflated by an aggregate-bandwidth bottleneck model that ignores mesh asymmetry. read the letter →

arxiv 2505.00041 v2 pith:MKFBHJDW submitted 2025-04-29 cs.AR

Ritik Raj , Shengjie Lin , William Won , Tushar Krishna This is my paper · ORCID

classification cs.AR

keywords multi-chipmoduleschipletacceleratorsend-to-endcommunicationnetwork-on-packageworkloadpartitioninghardware-softwareco-designenergy-delayproductmixed-integerquadraticprogramming

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Multi-chip-module (MCM) AI accelerators split a single large chip into smaller chiplets, which helps yield and cost but makes data movement between chiplets and off-chip memory a dominant part of latency and energy. This paper argues that the solution is to optimize the whole end-to-end communication path jointly rather than layer by layer: model congestion and packaging, then co-design the hardware (diagonal package links, on-package redistribution) with the software (non-uniform workload partitions, fine-grained pipelining). It formulates the resulting optimization as a scheduling problem and solves it with a genetic algorithm (GA) and with mixed-integer quadratic programming (MIQP). The reported gains over a uniform layer-sequential baseline are up to 35% and 142% geometric-mean latency improvements with GA and MIQP, and up to 1.58x and 2.7x energy-delay-product improvements, respectively. If the model is faithful, this would mean chiplet accelerators can become substantially more efficient without changing the underlying systolic-array compute cores.

What carries the argument

The central object is the end-to-end cost function $\mathrm{Cost} = \mathrm{Sche}(\{\mathrm{comp}(\ast_i), \mathrm{comm}(\ast_i) \mid i \in [N]\})$ over a sequence of GEMMs, where each operator's cost depends on the hardware configuration, the per-chiplet row and column partitions $P_x^i[x]$ and $P_y^i[y]$, and a fixed communication strategy. Per-chiplet compute follows the output-stationary systolic-array equation from SCALE-Sim, and off-chip communication is modeled in two steps: output collection is compressed to the aggregate bandwidth of the NoP links entering the global chiplet ($M_i N_i / (\text{bandwidth to entrances} \times BW_{nop})$), while input distribution uses hop-count formulas that differ for low-bandwidth DRAM and high-bandwidth HBM cases. The hardware optimizations enter as modified hop counts (diagonal links), a three-step row-reduce/broadcast/redistribute pattern (on-package redistribution), and an RCPSP-based schedule that overlaps communication with computation across samples. The machinery's job is to reduce end-to-end scheduling to an optimization problem whose variables are the workload partitions, so that GA can explore it approximately and MIQP can solve it more exactly.

What would settle it

Measure AlexNet and ViT inference on a real 4x4 chiplet system, or a cycle-accurate simulator, under uniform layer-sequential, greedy distance-proportional, GA, and MIQP partitions; then vary NoP and memory bandwidth and check whether observed latencies track Eq. (8)'s aggregate-bandwidth prediction. If the MIQP/GA gains vanish or the bottleneck shifts to links the model treats as free, the reported 2.7x is a property of the model, not the silicon.

Watch

Extended reading notes

Core claim

MCMComm's central claim is that the inter-chiplet communication bottleneck in MCM accelerators should be attacked with a packaging-adaptive, congestion-aware model of the entire operator sequence, not with layer-by-layer greedy partitioning. The paper defines four packaging types (2.5D corner memory, 2.5D distributed memory, 3D memory-on-logic, and hybrid 3D+2.5D) and shows that the same partition choices have different costs in each. It then adds hardware mechanisms -- diagonal NoP links that widen the congested paths toward memory, and on-package redistribution that reshapes GEMM outputs directly between chiplets -- and software mechanisms -- non-uniform row/column partitions and sample-level pipelining -- all inside the layer-sequential scheduling space. GA and MIQP solve the resulting cost model; MIQP uses an approximation that turns variable denominators into numerators so the equations fit a quadratic integer program. The paper reports that MIQP reaches up to 2.7x energy-delay-product improvement and GA up to 1.58x over uniform layer-sequential mapping, with the largest gains on sequentially chained CNNs such as AlexNet.

Load-bearing premise

The load-bearing premise is that the analytical model mirrors real MCM communication, especially the assumption that gathering outputs is bottlenecked by the total bandwidth of links entering the memory-attached chiplet.

Editorial extensions

If this is right

End-to-end co-optimization can beat both uniform partitioning and greedy distance-proportional partitioning; the SIMBA-like heuristic in the paper is reported to be no better than uniform layer-sequential, while GA and MIQP improve on it.
The gains are not limited to one package design: the framework reports improvements across all four packaging types and across 4x4, 8x8, and 16x16 chiplet grids.
Sequentially chained CNNs such as AlexNet benefit most from on-package redistribution, so the biggest wins are available in workloads where every operator consumes the previous operator's output directly.
The choice of solver matters: MIQP is slower (minutes versus seconds) but can reach substantially better solutions than the genetic algorithm, especially when the objective is EDP.
Fine-grained pipelining maintains its per-sample speedup across batch sizes, so the communication-computation overlap scales with inference batches.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

Editorial inference: the same cost-model machinery could be used at design time to choose memory placement and link topology before fixing a workload, not only to partition a given workload; the paper's packaging types make this a natural next step.
Editorial inference: the fixed communication strategies (e.g., sending farthest rows first) are approximations, and a dynamic or congestion-routing-aware strategy might close the remaining gap between GA and MIQP, especially on topologies where the global-chiplet links are not the only bottleneck.
Editorial inference: a direct testable extension would be to run the optimization under a full network simulator, replacing Eq. (8)'s aggregate-bandwidth approximation with per-link contention, to see which part of the reported 2.7x survives real packet-level congestion.
Editorial inference: because grouped GEMMs (attention heads) benefit less from redistribution, the framework's gains may concentrate in MLP and convolutional layers; explicit handling of grouped GEMMs is a possible path to extend the method to transformer-heavy workloads.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

The headline is that MCMComm is a serious modeling-and-optimization framework for chiplet communication, but its headline numbers come from an unvalidated analytical model, and there's a specific flaw in the data-collection equation that likely inflates the reported gains. The paper deserves a thoughtful referee, though, because the problem it tackles is real and the combination of ideas is new.

What's new: the framework is packaging-adaptive (four types of memory placement), separates low- and high-bandwidth memory congestion, and adds diagonal NoP links and on-package redistribution to the optimization space. The equations are explicit, which makes the model auditable, and the ablation study cleanly isolates the contributions of diagonal links and pipelining. The GA/MIQP schedulers are a reasonable way to explore the large partition space, and the comparison to SIMBA-like heuristics is useful.

The main soft spot is Eq. 8. It computes output-collection latency as total output bytes divided by the aggregate bandwidth of the links entering the global chiplet. That treats the two entrance links as a shared pool, but on a mesh they are not equally loaded. For a 4x4 type-A system with the global chiplet in a corner, the vertical entrance link carries output from three rows while the horizontal link carries only one row; under dimension-order routing the bottleneck is 1.5x the aggregate-bandwidth estimate. Non-uniform partitions can make it worse. Since output collection is one of the primary costs the framework optimizes, this bias flows into the optimal partitions and the reported EDP/Latency speedups. Also, Eq. 8 is derived for type A but applied to all four packaging types, and the 'waiting hops' strategy in Eq. 11 assumes a congestion resolution that is never validated against a network simulator or hardware.

The deeper issue is that the model is called 'cycle-accurate' but is entirely analytical. There is no comparison against ASTRA-sim, SCALE-Sim (beyond the compute equations), or any RTL. The MIQP formulation is also under-specified: the pseudocode is high-level, and the division-by-variable approximation comes with a caveat that it only holds near the expansion point. No artifacts or code are released.

None of these are deal-breakers; they are fixable with validation, a corrected bottleneck model, and a fuller MIQP description. But as it stands, the central claims are properties of the model, not of real hardware.

Who is this for? Researchers working on chiplet-based AI accelerators, NoP design, and hardware-software co-design will find the modeling framework worth reading, especially the packaging taxonomy and the diagonal-link idea. It deserves a serious referee after major revision, with validation required.

My recommendation: engage with it—but treat the numbers as hypotheses, and push the authors to validate the model against a cycle-accurate network simulator and release the artifacts.

Referee Report

5 major / 5 minor

Summary. This paper presents MCMComm, an analytical framework for end-to-end latency and energy-delay-product modeling of multi-chip-module (MCM) processors running DNN workloads under layer-sequential scheduling. The framework models compute with SCALE-Sim-style output-stationary equations, off-chip transfers through main-memory bandwidth, and on-package transfers through hop counts and congestion-aware formulas that depend on package type (A-D). On top of the model, the authors propose hardware-software co-optimizations: diagonal NoP links, on-package output redistribution, and sample-level pipelining, and they solve the resulting scheduling and partitioning problem with a genetic algorithm and an MIQP formulation. The evaluation reports normalized latency and EDP improvements versus uniform layer-sequential baselines across AlexNet, ViT-B, ViM-S, Hydranet2, and Llama7B on 4x4, 8x8, and 16x16 chiplet systems with HBM and DRAM, claiming up to 2.7x EDP improvement with MIQP.

Significance. If the analytical model were validated, the paper would be a useful contribution: it makes congestion- and packaging-aware communication modeling explicit for MCMs, proposes concrete co-design mechanisms (diagonal links, on-package redistribution, fine-grained pipelining), and provides explicit optimization machinery in the form of GA and MIQP. The cost equations are stated and none of the reported speedups come from fitting parameters, which is a strength. However, the significance as stated rests entirely on the analytical model: there is no validation against a cycle-accurate network simulator, RTL, or hardware measurement, and the model itself contains a load-bearing simplification in the data-collection term (Section 4.3.2, Eq. 8). The claimed 1.58x and 2.7x EdP improvements are therefore currently properties of the model rather than demonstrated properties of the hardware.

major comments (5)

[Section 4.3.2, Eq. (8)] The output-collection latency is computed as M_i*N_i divided by the aggregate bandwidth of the links entering the global chiplet(s). The derivation is restricted to a type-A corner-global system, yet Section 7 reports results for types B, C, and D using the same framework. Even within type A the formula is not congestion-safe: with dimension-order routing on a 4x4 mesh, the vertical link into the corner global chiplet carries output from the three rows with y>0 while the horizontal link carries only the y=0 row, so the bottleneck time is 3T/(4B) rather than T/(2B) for uniformly distributed output. Optimized non-uniform partitions can shift this imbalance further. Because this term is the primary target of the diagonal-link and redistribution optimizations, the claimed EdP gains may partly reflect an understated bottleneck. Please generalize the model to routing and congestion behavior or validate it with a network simulator.
[Section 4.3.3, Case 2.1, Eqs. (11)-(12)] The fixed communication strategy inserts a waiting-hops term (X-x for row-wise shared data, Y-y for column-wise shared data) that assumes a specific congestion-resolution order, namely sending the farthest row or column first. No derivation or simulation is given for this assumption, and the paper's own motivation in Section 3.2 uses ASTRA-sim but the model itself is never compared against ASTRA-sim or any other NoP simulator or hardware trace. Since this term determines the cost of input distribution and is used by both GA and MIQP, an incorrect waiting-hop model can bias the optimized partitions. Please provide validation data or a derivation of the waiting-hop count.
[Section 5.1] Diagonal links are modeled as providing 50% more bandwidth on the bottleneck links, with no area, pin-out, routing, or energy overhead included beyond hop count. No physical implementation or cost data are given for these links, and the ablation study in Figure 13 attributes a large fraction of the speedup to them. Because the optimization is performed against this cost model, the framework is biased toward an infrastructure whose real cost is unknown. Please add a physical-design cost model or at least a sensitivity analysis over diagonal-link cost and energy.
[Section 6.3.1] The MIQP formulation replaces divisions by variable denominators with the first-order approximation 1/(c+x) approximately (c-x)/c^2, and the text acknowledges that the approximation is accurate only when x is close to c. No evidence is provided that the partition variables remain close to the hardware parameters for the workloads explored in Section 7. Since the MIQP solutions are used to claim near-optimality over GA, the approximation error should be quantified over the explored partition space, or the final MIQP schedules should be re-evaluated with the exact analytical objective.
[Section 4 as a whole] The paper describes the framework as cycle-accurate in Figure 1 and the introduction, but the network-latency and congestion equations are analytical formulas that are not validated against a cycle-accurate NoP simulator, RTL, or hardware. The compute portion follows SCALE-Sim, but the off-package and NoP terms are the paper's own. Without a comparison of predicted end-to-end latency and energy to a simulator such as ASTRA-sim (which the authors already use in Section 3.2) for at least type-A and type-B systems, the numerical results should be reported as model-based predictions rather than as measured improvements.

minor comments (5)

[Abstract and Section 7.2] The abstract states up to 1.58x and 2.7x EdP improvement using GA and MIQP, respectively, while Section 7.2 reports geomean EDP improvements of up to 37% and 72%; please clarify whether the abstract reports per-model maxima rather than geomeans.
[Eq. (8) notation] The output-collection equation in Section 4.3.2 is not numbered and its denominator reads bandwidth to entrances multiplied by BW_nop; please define the number of entrance links and the aggregation operation explicitly so the equation is self-contained.
[Table 2 and Section 4.3.3] Table 2 sets both DRAM bandwidth and NoP bandwidth to 60 GB/s, while Section 4.3.3 describes the low-bandwidth case as having off-chip bandwidth lower than NoP bandwidth; please clarify how the equality condition is modeled.
[Throughout] The text contains typos such as fined-grained in Section 5, Pprogramming in the introduction, they are they result in sub-optimal in Section 3.5, and monolithically non-increase in Section 4.3.2; these should be corrected.
[Conclusion] The conclusion mentions mixed integer linear programming, but the body and Section 6.3 use mixed integer quadratic programming; please make the terminology consistent.

Circularity Check

0 steps flagged · score 1.0 of 10

No significant circularity: the reported speedups come from optimizing and then re-evaluating the same analytical cost model, with only minor, non-load-bearing self-citations.

full rationale

MCMComm's derivation chain is a stated analytical latency and energy model (Eqs. 7-12, Section 4.3-4.4) that is used both as the optimization objective for GA/MIQP and as the evaluation metric for the reported 1.58x and 2.7x EdP improvements. This is closed-loop model-based design-space exploration, not circular derivation: no parameter is fitted to force the reported numbers, and the optimizer searches a large constrained partition space rather than reading the answer directly from the model. The self-citations are not load-bearing: SCALE-Sim timing is externally published in [55] as well as in the authors' v3 [53], ASTRA-sim is an independent network simulator used only for motivational experiments, and Concerto [12] is cited only to recognize RCPSP, a classic scheduling problem. The genuine weaknesses are validation fidelity issues, not circularity: Eq. 8 aggregates all output collection into the bandwidth of links entering the global chiplet and is explicitly derived for type A while Section 7 reports results for all four packaging types, and the fixed congestion-resolution strategy behind Eq. 11 is an unvalidated modeling assumption. These could bias the EdP gains if the model under-estimates NoP congestion, but that is a correctness risk rather than a circular step. Therefore no circular step meets the evidence bar established by the review rules.

Assumptions & free parameters 5 free parameters · 7 assumptions · 1 invented entities

The framework's cost functions are explicit and not fitted to the reported speedups, so the ledger is mostly assumptions and inputs: energy constants, link serialization, fixed communication strategies, cost-free diagonal links, and an unvalidated MIQP linearization. The central model-based results inherit every one of these assumptions.

free parameters (5)

c_SRAM energy constant = 0.28 pJ/bit
Energy-model input in Table 2 used in Eq. (4.4.1) EDP calculation; no source cited, hand-chosen value affects reported EDP gains.
c_MAC energy constant = 4.6 pJ/cycle
Per-MAC energy used in Eq. (4.4.1); no source cited in the paper.
c_NoP energy constant = 1.285 pJ/bit/hop
On-package link energy used in Eq. (4.4.3); no source cited; directly weights diagonal-link tradeoffs.
c_off-chip energy (DRAM/HBM) = 14.8 pJ/bit (DRAM), 4.11 pJ/bit (HBM)
Off-chip energy constants in Table 2; no source cited, but the relative priority of off-chip versus NoP energy depends on them.
MIQP constant scaling factor = unspecified
Section 6.3.1 says all equation values are shrunk by a 'properly chosen' factor to avoid integer overflow; the value is not given and the paper admits it introduces precision error.

assumptions (7)

domain assumption SCALE-Sim output-stationary cycle equation (Eq. 7) is cycle-accurate for chiplet compute.
Borrowed from a prior simulator without re-derivation; used as ground truth for compute time.
domain assumption Each chiplet communicates only with the closest global chiplet.
Section 4.2.1 states: 'we assume that each chiplet will only communicate with the closest global chiplet.'
domain assumption NoP links cannot be shared by two data transfers at the same time.
The evaluation section states this serialization; it underlies hop-count and contention equations.
domain assumption Workload assigned to a chiplet monolithically non-increases with distance from memory in type A systems.
Section 4.3.2 uses this observation to justify the offloading bottleneck formula Eq. 8; optimized non-uniform partitions may violate it.
domain assumption A fixed communication strategy (farthest-row-first, row or column broadcast) is near-optimal and sufficient.
Section 4.3.3 says 'we adopt a fixed communication strategy' to keep interactions tractable.
ad hoc to paper MIQP division approximation 1/(c+x) ~ (c-x)/c^2 is accurate for the workload partitions explored.
Section 6.3.1 introduces the approximation; the paper says it is effective only near the expansion point but gives no error bound.
ad hoc to paper Diagonal links can be added to the package with no area, cost, or added energy overhead beyond hop count.
Section 5.1 models only bandwidth and hop count of diagonal links; no physical implementation cost is included in the objective.

invented entities (1)

Diagonal NoP links
purpose: Add extra paths into the global chiplet to relieve entrance-link congestion in data collection and distribution.
Proposed hardware feature evaluated only through the paper's analytical hop-count model; no fabricated test chip, simulator validation, or area/power estimate is provided.

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Cite this review

Pith. "Pith review of MCMComm: Hardware-Software Co-Optimization for End-to-End Communication in Multi-Chip-Modules." pith.science (2026). https://pith.science/paper/MKFBHJDW

@misc{pith2026250500041,
  author       = {Pith},
  title        = {Pith review of: MCMComm: Hardware-Software Co-Optimization for End-to-End Communication in Multi-Chip-Modules},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/MKFBHJDW}},
  note         = {Machine review of arXiv:2505.00041}
}

read the original abstract

Increasing AI computing demands and slowing transistor scaling have led to the advent of Multi-Chip-Module (MCMs) based accelerators. MCMs enable cost-effective scalability, higher yield, and modular reuse by partitioning large chips into smaller chiplets. However, MCMs come at an increased communication cost, which requires critical analysis and optimization. This paper makes three main contributions: (i) an end-to-end, off-chip congestion-aware and packaging-adaptive analytical framework for detailed analysis, (ii) hardware software co-optimization incorporating diagonal links, on-chip redistribution, and non-uniform workload partitioning to optimize the framework, and (iii) using metaheuristics (genetic algorithms, GA) and mixed integer quadratic programming (MIQP) to solve the optimized framework. Experimental results demonstrate significant performance improvements for CNNs and Vision Transformers, showcasing up to 1.58x and 2.7x EdP (Energy delay Product) improvement using GA and MIQP, respectively.

Figures

Figures reproduced from arXiv: 2505.00041 by the authors.

**Figure 1.** MCMComm system with NPU-based chiplets, challenges, and key ideas, optimized LS scheduling space, and real-time applications [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗

**Figure 2.** MCMComm framework with genetic algorithm and non-integer programming schedulers showing different input knobs. The framework is packaging-adaptive as shown by four types of chiplets showing different positions of main memory (DRAM/HBM) in 2.5D and 3D packaging. The framework separately models high-BW and low-BW off-chip cases making it congestion-aware. algorithm called Simulated Annealing (SA). Additionally, the HW… view at source ↗

**Figure 3.** Modeling results when all chiplets are pulling 1 GB message from the memory over a 4×4 Mesh. Node 16 denotes the memory node. DRAM/HBM bandwidth is 60 GB/s and 1,024 GB/s, and Low/High NoP link bandwidth is 60 GB/s and 120 GB/s, respectively. (a)–(c) Network utilization heat map with different memory types and placements, when NoP bandwidth is 60 GB/s. (d) Total network communication latencies. of HBM in [PITH_FUL… view at source ↗

Figures from the paper (7 more)

**Figure 4.** Figure 4: Illustration of chiplet topology for 4 types of systems. The dashed lines represent chiplet allocation results. Each chiplet has a local index (x, y). 4.2.4 Scheduling Problem. Given configurations in Section 4.2.1, workload definition in Section 4.2.2 and allocation …

**Figure 5.** Figure 5: Illustration of Congestion during data collection and effects of diagonal links. 4.3.1 Computation. Compute is modeled by the output stationary dataflow [11, 61]. Following cycle-accurate equations described in SCALE-Sim [53, 55], the latency cost for computation in a…

**Figure 6.** Figure 6: Three-step on-package data redistribution process. Arrows of different colors represent different communication steps. Inp W1 Op1 Inp W1 Out1 Op1 W2 Op2 Out1 W2 Op2 Comm Comp Comm Comp Time Saved W1 Op1 Out1 W2 Op2 Inp W1 Op1 Out1 W2 Op2 [PITH_FULL_IMAGE:figures/full…

**Figure 8.** Figure 8: Latency comparison of MIQP and GA over the baseline for High Bandwidth (HBM) case. Results are normalized. Alexnet ViT-B ViM-S Hydranet2 Llama7B (Geometric Mean) 4x4 0 1 2 Normalized Latency 0.99 0.99 0.99 0.99 1.00 0.99 1.18 1.10 1.11 1.20 1.07 1.13 1.84 1.40 1.53 1.3…

**Figure 11.** Figure 11: Performance of pipelining given different batch sizes. Alexnet ViT-B ViM-S Hydranet2 Llama7B (Geometric Mean) 4x4 0 1 2 Normalized Latency 1.04 1.03 1.07 1.06 1.01 1.04 1.48 1.26 1.31 1.24 1.14 1.28 1.79 1.29 1.49 1.31 1.17 1.40 LS SIMBA-like GA MIQP (a) Latency Alexn…

**Figure 9.** Figure 9: Latency comparison of MIQP and GA over the baseline for High Bandwidth case, type-A system. Results are normalized. Alexnet ViT-B ViM-S Hydranet2 Llama7B (Geometric Mean) 4x4 0 1 2 EDP Efficiency 0.95 1.00 1.00 0.99 1.00 0.99 1.35 1.17 1.20 1.34 1.08 1.22 2.08 1.43 1.6…

**Figure 13.** Figure 13: Ablation study on diagonal links and pipelining. 8 Conclusion In this paper, we addressed the challenges of optimizing endto-end communication and workload partitioning in MCM accelerators. We proposed a cycle-accurate, congestion-aware, 11 [PITH_FULL_IMAGE:figures/…

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