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REVIEW 4 major objections 5 minor 48 references

MMStencil: Optimizing High-order Stencils on Multicore CPU using Matrix Unit

T0 review · 4 major / 5 minor · reviewed 2026-08-06 · deepseek-v4-flash

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Pith's one-line read MMStencil shows a RISC multicore CPU's outer-product matrix unit can outperform an Nvidia A100 GPGPU by up to 2.1x on 3D high-order stencils and speed up reverse-time-migration imaging by 1.8x.

desk verdict The matrix-unit mapping for 3D high-order stencils is real and worth engaging; the CPU-vs-GPU speedups are not yet established because the comparisons mix precision and grid sizes. read the letter →

arxiv 2507.11067 v1 pith:NPZBV2NC submitted 2025-07-15 cs.DC

Yinuo Wang , Tianqi Mao , Lin Gan , Wubing Wan , Zeyu Song , Jiayu Fu , Lanke He , Wenqiang Wang
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Zekun Yin Wei Xue Guangwen Yang
This is my paper · ORCID
classification cs.DC
keywords stencilcomputationmatrixunitouterproductmulticoreCPUhigh-orderReverseTimeMigrationNUMASDMA
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

MMStencil claims that a RISC multicore CPU's outer-product matrix unit can make 3D high-order stencil computations—the kind that dominate seismic imaging and other PDE solvers—run faster than they do on an Nvidia A100 GPGPU. By recasting each stencil axis as a sequence of outer products, reorganizing the grid into bricks to keep memory streams contiguous, serving halo data from neighboring cores' private caches instead of main memory, and using the chip's DMA engine for cross-NUMA halo exchange, the paper reports up to 2.1x speedup over state-of-the-art GPU libraries on stencil kernels and a 1.8x speedup in an end-to-end Reverse Time Migration workload. If true, this would mean CPUs with matrix units can rival or beat GPGPUs on an important memory-bound HPC kernel class, without giving up CPU programmability. The paper also reports that the same techniques hold up when scaling from one NUMA node to a full two-socket server.

What carries the argument

The load-bearing mechanism is the outer-product mapping of a stencil onto the matrix unit: a one-dimensional stencil of radius r is computed by loading input vectors and outer-producting them with coefficient columns into a [VL x VL] matrix tile accumulator, with the axes composed in sequence for 3D. Around it, the paper stacks four supporting mechanisms: tile-based instruction-level parallelism that interleaves outer products across matrix tiles; a tile-assisted vector transpose that uses horizontal loads and vertical stores to avoid gather penalties along the x-axis; a brick memory layout (with brick sizes chosen to match the vector length and stencil radius) that reduces the number of concurrent memory streams; and a cache-snoop scheme where adjacent tiles are assigned to adjacent cores so halo regions are served from peer L2 caches, plus gather-based software prefetch and SDMA-based asynchronous halo exchange for multi-NUMA scaling.

What would settle it

Run the 3D radius-4 star stencil in the same precision (single or double) on the same grid size ($512^{3}$) on both the disclosed RISC CPU with MMStencil and an NVIDIA A100 with the best available CUDA stencil library, using the same halo-exchange and tiling constraints; if the CPU fails to beat the GPU, or the RTM speedup disappears when both run $512^{3}$ grids, the central claim is not established.

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Extended reading notes

Core claim

The paper's central discovery is that high-order 3D stencils, which degrade SIMD and CUDA implementations, map naturally onto outer-product matrix units: each axis of the stencil becomes a series of outer products between a vector loaded from the input and a coefficient vector, accumulated in matrix tiles. With 512-bit SIMD registers and a 16x16 matrix tile, the instruction count grows as (VL + 2r) outer products instead of VL x (2r+1) SIMD FMAs, which flips the balance in favor of the matrix unit as soon as the stencil radius exceeds one. The paper combines this mapping with a brick memory layout borrowed from prior blocked-stencil work, cache-snoop-based halo sharing between cores that lack a shared last-level cache, and SDMA-engine-based asynchronous halo exchange to replace MPI, and reports that the combination sustains high hardware utilization across stencil shapes and scales to outperform an A100 GPGPU by up to 2.1x on kernels and 1.8x on an industrial reverse-time-migration application.

Load-bearing premise

The headline speedups assume the CPU and GPU runs are fairly comparable: the CPU runs single precision on an undisclosed RISC chip, the GPU baselines mostly run double precision, the RTM workload uses a smaller grid on the CPU, and one flagship CPU baseline library could not be run at all; if those imbalances were corrected, the claimed margins might shrink.

Editorial extensions

If this is right

  • If the mapping is right, high-order stencil kernels—the hard case for SIMD and CUDA—become the sweet spot for CPU matrix units, with speedups growing as stencil radius increases.
  • The brick layout plus cache-snooping could let stencil codes run at near-peak on-package memory bandwidth on multicore CPUs without a shared last-level cache.
  • SDMA-based halo exchange, with pipeline overlap, removes MPI's shared-memory locking bottleneck and makes hybrid MPI+OpenMP scaling practical on multi-die CPUs.
  • CPU-based RTM and similar seismic imaging workloads could reach or exceed GPU throughput on CPU-only servers, simplifying deployment of industrial HPC codes.
  • The paper's performance model suggests the technique carries over to any matrix unit with sufficiently low outer-product latency, not just the specific chip used.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The same outer-product decomposition should transfer to other matrix-unit CPUs or future tensor-core hardware; the paper's own performance model gives a quick formula for predicting where it wins.
  • The cache-snoop halo scheme suggests a general principle for multicore SoCs without shared last-level caches: assign adjacent tiles to adjacent cores and let the coherence protocol serve halo data, which could extend to other halo-exchange PDE solvers.
  • A natural extension is to exercise the matrix unit's full-precision path—the paper runs single precision—by benchmarking double-precision stencils, and to combine the brick layout with temporal blocking.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 5 minor

Summary. The paper presents MMStencil, a framework for accelerating 3D high-order stencil computations on a RISC multicore CPU with an outer-product matrix unit. The contributions are: a mapping of 1D stencils to outer-product matrix operations; microarchitectural techniques such as tile-based ILP, tile-assisted vector transpose, cache-pollution-avoiding intermediate placement, and a redundant-access-zeroing box-stencil scheme; memory optimizations consisting of a SIMD-friendly brick layout and gather-based software prefetch; a cache-snoop-based data-sharing scheme for cores without a shared LLC; and SDMA-based halo exchange for multi-NUMA and MPI settings. The authors integrate the kernels into RTM applications and report speedups over SIMD baselines on the CPU and, as headline claims, up to 2.1x over state-of-the-art GPU libraries on an NVIDIA A100 and a 1.8x speedup over an industrial A100 RTM implementation.

Significance. If the headline claims are substantiated, the paper would demonstrate that CPU matrix units combined with on-package memory can beat GPGPUs on an important memory-bound kernel class, which would be a meaningful result for the HPC community. The paper also provides useful algorithmic ideas, particularly the outer-product stencil mapping and the cache-snoop/SDMA parallelization techniques, and it includes a performance breakdown (Fig. 12) that gives insight into which optimizations matter. However, the headline CPU-versus-GPU speedups rest on comparisons that are not apples-to-apples, and the CPU platform is undisclosed, so the quantitative claims are not yet established.

major comments (4)
  1. [Sec. V-C, V-E3; Sec. III-B.d] The headline 2.1x speedup over GPU libraries is based on a precision mismatch that is load-bearing for a memory-bound kernel. Sec. III-B.d states that all GPU libraries run in double precision (except TCStencil in half precision) while CPU libraries run in single precision, and the main comparisons in Fig. 11 and the weak-scaling result in Sec. V-E3 report wall-clock or speedup ratios without normalizing for datatype width. For a memory-bound stencil, DRAM traffic scales with the datatype size, so an FP32 CPU kernel moves half the bytes of an FP64 GPU kernel. The Bandwidth Utilization metric defined in Sec. III-B.d normalizes by sizeof(datatype), but the claimed 2.1x is a raw wall-clock ratio. The authors should rerun the GPU baselines in single precision at the same grid size (or otherwise provide a precision-normalized comparison) before claiming a CPU-over-GPU speedup.
  2. [Sec. V-F] The RTM comparison is not workload-normalized. Sec. V-F sets the CPU grid to (512, 512, 256) 'due to on-package memory capacity limitations' while the GPU grid is (512, 512, 512), so the GPU executes twice as many grid points. The abstract's 1.8x speedup and the Sec. V-F scaling claim of up to 3.5x speedup over the CUDA implementation therefore conflate workload reduction with performance advantage. The authors should either run the same problem size on both platforms or report per-point or per-unit-work throughput (e.g., stencils per second per grid point).
  3. [Sec. V-A; Sec. II-B footnote 1] The CPU platform is undisclosed, and the CPU baseline set is incomplete, which weakens the 'outperforms state-of-the-art libraries' claim. Footnote 1 in Sec. II-B states that hardware specifications cannot be disclosed, and Sec. V-A footnote 2 says BrickLib's CPU implementation could not run and that the authors instead implemented their own SIMD baseline. The paper cites Yask [18] and Devito [20] but does not compare against them. While the kernel techniques may be sound, the absence of a disclosed platform and the lack of well-established CPU stencil baselines make it impossible to assess whether the reported CPU performance is a property of the algorithm or of an unusual, unreproducible platform. At minimum, the authors should provide a detailed enough description (or a known equivalent) and add at least one independently maintained CPU stencil baseline.
  4. [Sec. IV-B; Sec. V-D] The performance model in Sec. IV-B is not used as a predictive tool, and its discrepancy with the measured results is not explained quantitatively. The model predicts a theoretical 1.5x speedup for r=4, but Sec. V-D attributes the larger measured gains to qualitative factors such as instruction-scheduling overhead. The paper would be stronger if the experiments tested the model's predictions across a range of radii and precisions, or if the model were revised to account for the scheduling effects. As written, the model is an incentive device rather than evidence for the central claim, though this is not a fatal flaw on its own.
minor comments (5)
  1. [Abstract and throughout] There are several typographical errors, including 'Nividia' (Abstract), 'absense' (Sec. I and II-A), and 'Intermedian' (Sec. IV-C heading). The paper would benefit from a careful proofread.
  2. [Sec. V-A] The classification in Table I labels 3DBoxR2 as 'Computation Bound,' but Sec. V-B says the kernel is 'compute-bound' and Sec. V-C reports 85% of the 3.75 TFLOPS theoretical peak. This is consistent, but the table does not state the peak FLOPS or memory bandwidth used for the Roofline classification; adding those numbers would improve interpretability.
  3. [Sec. V-E2] The sentence 'MMStencil matches the CUDA performance' in Sec. V-E2 compares against BrickLib running the 3DStarR4 stencil in single precision on the A100. This is a more controlled comparison than the rest of the paper, but the result is reported without a timing table or precision statement for MMStencil; please clarify that the comparison is single-precision on both sides and report the actual runtimes.
  4. [Fig. 14 and Fig. 15] The captions for Fig. 14 and Fig. 15 do not define the axes or the baseline curves. In particular, Fig. 15 is described as 'RTM Scaling Experiments' but the caption does not state whether the y-axis is elapsed time or speedup, or what the 'CUDA' curve represents. Please make the captions self-contained.
  5. [Sec. IV-B] The notation 'CPI Matrix = 2in single precision' in Sec. IV-B should read '2 in single precision' to avoid confusion. Also, the derivation of Cycles_Matrix = (VL + 2r) * CPI_Matrix assumes one outer product per stencil offset; this should be stated explicitly.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the central performance claims are direct measurements against external baselines; the only self-citations are domain background or non-load-bearing.

full rationale

The paper's derivation chain is not circular. The stencil-to-matrix-unit mapping (Sec. IV-A) is a constructive algorithm, and the performance model (Sec. IV-B) is an analytic instruction-count/CPI estimate: it uses stated hardware constants (CPI_SIMD=0.5, CPI_Matrix=2) and is not fitted to the later speedups. The headline CPU-vs-GPU results (Sec. V-C, V-E, V-F) are measured wall-clock comparisons against external baselines (BrickLib, EBISU, TCStencil, LoRAStencil, ConvStencil, compiler and hand-tuned SIMD code), not predictions derived from the model. The only same-author citations are [7] and [9]: [7] is domain background on earthquake simulation, and [9] is cited in Sec. IV-F for a pipeline-overlap scheme alongside the independent Pencil reference [45]; neither is used to establish the central claim or to exclude alternatives. No uniqueness theorem is imported, no fitted parameter is renamed as a prediction, and no known result is merely relabeled. The principal weaknesses—undisclosed CPU platform details (Sec. II-B footnote), the unavailable BrickLib CPU port (Sec. V-A footnote), and unequal precision/grid sizes in some GPU comparisons (Sec. V-F)—are experimental-fairness and transparency issues, not circular derivation.

Assumptions & free parameters 2 free parameters · 4 assumptions · 0 invented entities

The paper introduces no new physical entities; the free parameters are engineering choices (tile sizes) and hardware CPI values. The load-bearing assumptions are about the undisclosed platform's microarchitecture and about the fairness of cross-precision, cross-size benchmarks. The count of assumptions is small, but their unverifiability is the main obstacle to accepting the claims.

free parameters (2)
  • Block and brick tile sizes (VX, VY, VZ; BX, BY, BZ) = VX=VY=16, VZ=4 or multiples; BX=VL, BY=BZ=4
    Chosen by hand in Sec IV-D and Table I to balance contiguous access, halo traffic, and matrix-tile ILP; the choices directly affect the measured performance and are not derived from the stencil equations.
  • Matrix unit CPI and SIMD CPI = CPI_Matrix=2, CPI_SIMD=0.5 (single precision)
    Hardware measurements quoted in Sec IV-B and used in the theoretical speedup model; they are inputs, not fit to the results, but they are unverifiable without platform disclosure.
assumptions (4)
  • domain assumption The experimental CPU's Matrix unit executes outer products at CPI=2 with 4-cycle latency and saturates with interleaved tiles.
    Used in Sec IV-B performance model and Sec V-D to explain why Matrix unit beats SIMD; cannot be checked without platform details.
  • domain assumption The CPU cores have private data caches but no shared last-level cache; coherence snooping can serve halo data from neighboring cores.
    Motivates the cache-snoop data-sharing scheme in Sec IV-E; if a shared LLC exists on the platform, the scheme's benefit and the premise are false.
  • ad hoc to paper Normalizing by sizeof(datatype) in the bandwidth-utilization metric makes single-precision CPU and double-precision GPU comparisons fair.
    Introduced in Sec III-B; the metric does not account for precision-dependent arithmetic throughput on GPUs, so the fairness of cross-precision comparisons rests on this assumption.
  • domain assumption Single precision is the appropriate working precision for RTM, so CPU single-precision results are directly comparable to the industrial GPU implementation.
    Sec II-B states RTM relies on single precision; if the industrial GPU code uses higher precision or a different algorithm, the RTM speedup comparison is invalid.

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Cite this review

Pith. "Pith review of MMStencil: Optimizing High-order Stencils on Multicore CPU using Matrix Unit." pith.science (2026). https://pith.science/paper/NPZBV2NC

@misc{pith2026250711067,
  author       = {Pith},
  title        = {Pith review of: MMStencil: Optimizing High-order Stencils on Multicore CPU using Matrix Unit},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/NPZBV2NC}},
  note         = {Machine review of arXiv:2507.11067}
}
read the original abstract

Matrix-accelerated stencil computation is a hot research topic, yet its application to three-dimensional (3D) high-order stencils and HPC remains underexplored. With the emergence of matrix units on multicore CPUs, we analyze matrix-based acceleration strategies and tailor an optimal approach for 3D high-order stencils. We introduce algorithmic optimizations based on SIMD and matrix units to address strided memory accesses, alignment conflicts, and redundant accesses. We propose memory optimizations to boost on-package memory efficiency, and a novel multi-thread parallelism paradigm to overcome data-sharing challenges caused by the absence of shared data caches. MMStencil sustains consistently high hardware utilization across diverse stencil shapes and dimensions. Our DMA-based inter-NUMA communication further mitigates NUMA effects and MPI limitations in hybrid parallelism. Combining all the innovations, MMStencil outperforms state-of-the-art libraries on Nvidia A100 GPGPU by up to 2.1x. Moreover, the performance improvements translate directly to real-world HPC applications and enable RTM applications to yield 1.8x speedup versus a highly optimized industrial Nvidia A100 GPGPU version.

Figures

Figures reproduced from arXiv: 2507.11067 by the authors.

Figure 1
Figure 1. Two Stencil Examples: Box and Star high-order stencils form a particularly crucial subclass, un￾derpinning many real-world high-performance computing ap￾plications [4], [7]–[9]. For instance, Reverse Time Migration (RTM), a pivotal supercomputing application for earth mod￾eling, employs finite difference methods for approximating spatial derivatives. To balance computational efficiency and storage demands, geophysic… view at source ↗
Figure 2
Figure 2. Outer-Product Based Matrix Compute Mechanism. [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Bandwidth Utilization of State-of-the-arts [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figures from the paper (12 more)
Figure 4
Figure 4. Figure 4: Mapping Stencil to Matrix Unit As shown in [PITH_FULL_IMAGE:figures/full_fig_p005_4.png]
Figure 5
Figure 5. Figure 5: Tile-Assisted Vector Transpose b) Tile-Assisted Vector Transpose: When computing the x-axis stencil, accessing each (1, VY , 1) column vector incurs non-contiguous memory accesses. As most modern CPUs perform 2 loads and 1 store per cycle, on a 512- bit SIMD platform, …
Figure 6
Figure 6. Figure 6: Redundant-Access Zeroing Box Stencil computational efficiency without incurring extra arithmetic overhead or imposing restrictions on the stencil properties. D. Memory Optimizations Stencil computations demand both high computational power and bandwidth. With our micro…
Figure 7
Figure 7. Figure 7: SIMD-Friendly Memory Reorder and Gather-Based [PITH_FULL_IMAGE:figures/full_fig_p007_7.png]
Figure 8
Figure 8. Figure 8: Cache-snoop based Data Sharing To address this limitation, we exploit the data cache coher￾ence protocol. Whenever a core accesses an address missing in its private caches, it checks the NUMA’s root directory. If the data resides in another core’s cache, it is retrieve…
Figure 9
Figure 9. Figure 9: Pipeline Overlapping Scheme Another advantage of the SDMA engine is its non-intrusive nature: it does not occupy CPU cores or pollute caches. This allows efficient computation–communication overlap. Specifically, we apply a pipeline-overlap scheme [9], [45] by partitio…
Figure 10
Figure 10. Figure 10: Computing partial derivatives c) Benchmarks: We selected eight stencil benchmarks with varying shapes and dimensions, as detailed in Tab. I. This set includes four star stencils (2DStarR2, 2DStarR4, 3DStarR2, 3DStarR4) and four box stencils (2DBoxR2, 2DBoxR3, 3DBoxR1,…
Figure 11
Figure 11. Figure 11: Performance Comparisons with Baselines [PITH_FULL_IMAGE:figures/full_fig_p010_11.png]
Figure 12
Figure 12. Figure 12: Performance Breakdown of MMStencil thereby validating our “Redundant Access Zeroing Box Stencil Optimization” scheme. In the case of 3D stencils, the SIMD intrinsic version surprisingly delivers the best performance for the 3DStarR2 kernel. Although 3DStarR2 exhibits …
Figure 13
Figure 13. Figure 13: Scaling Experiments of MMStencil 1) SDMA Communication Bandwidth Test: We first assess the data exchange bandwidth across NUMA nodes using both SDMA and MPI. The global grid size is set to 512×512×512, and two processes are placed on the same DDR die to perform the ha…
Figure 14
Figure 14. Figure 14: RTM Performance using MMStencil F. Performance in HPC Applications In this subsection, we evaluate the performance gains achieved by integrating MMStencil into complex HPC appli￾cations. Leveraging our expertise in earth modeling, we target RTM in both VTI and TTI med…
Figure 15
Figure 15. Figure 15: RTM Scaling Experiments industrially optimized RTM implementations for both CPU and GPU, as provided by Bureau of Geophysical Prospecting INC. China National Petroleum Corporation. The CPU version runs on the experimental platform, while the GPU version is executed on…

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Pith tools

Reviewed August 6, 2026 · model on record in the stance chip above.