Integrity report for Architectural improvements and 28 nm FPGA implementation of the APEnet+ 3D Torus network for hybrid HPC systems
A machine-verified record of the checks Pith has run against this paper: detector runs, findings, signed bundle events, and canonical identifiers.
0Critical
0Advisory
0Detectors run
—Last checked
Paper page arXiv integrity.json bundle.json
Detector runs
Findings
No public integrity findings for this paper.
Signed record
The machine-readable record for this paper lives at /pith/NVUHW4HL/integrity.json. Pith Number bundles also include signed pith.integrity.v1 events where a Pith Number exists.