REVIEW 4 major objections 5 minor 34 references
Beyond Static Policies: Dynamic Selection Among Modern Microarchitectural Policies
T0 review · 4 major / 5 minor · reviewed 2026-08-06 · deepseek-v4-flash
Pith's one-line read This paper argues that the eight-configuration memory-policy design space collapses to a one-bit L1D-prefetcher choice, and that practical runtime selectors can recover most of the resulting opportunity using only executed IPC or passively
desk verdict A useful first systematic look at policy composition with a striking compression result, but the headline recovery numbers are post-selection estimates and need a nested evaluation before I'd trust them. read the letter →
The pith
A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.
The reading
What carries the argument
The load-bearing mechanism is the policy selector block (PSB), a hardware block that emits one bit per 200K-instruction window choosing between Berti and Gaze while BARCA and PACIPV stay fixed. In the demand-based instantiation, the PSB materializes six counters from the demand stream during a 20% sampling prefix and traverses a frozen depth-3 decision tree, costing at most three threshold comparisons per window. In the executed-performance instantiation, a sliding-window UCB rule keeps short IPC histories per policy and occasionally retries the inactive prefetcher. The counterfactual upper bound is an idealized observer that reports the previous window's winner with controlled delay and err
What would settle it
On the 10 held-out traces, re-run the frozen tree with the six features computed over a mid-window 20% slice (instructions 80K to 120K) instead of the first 20%; if agreement with the first-prefix label is low, or if a selector using that prefix loses more than the reported 0.465%, the prefix-representativeness assumption is refuted.
Extended reading notes
Core claim
The paper's central claim is that the performance left behind by any fixed policy combination is both real and highly structured. Across 4,900 windows, the best global static policy, Gaze/Entangling/Mockingjay, wins 33.47% of phases but is 1.33% below the phase oracle on average. That opportunity collapses to a single binary choice: holding L1I prefetching and L2 replacement fixed, a Berti/Gaze pair that changes only the L1D prefetcher reproduces the full eight-configuration oracle's aggregate IPC to within 0.039%. Runtime selection is then an information problem: what can hardware know before choosing? The paper evaluates selectors by information tier and finds that executed-performance fee
Load-bearing premise
The load-bearing premise is that demand-stream features read from the first 20% of a 200K-instruction window predict which of Berti or Gaze will be better for the remainder of that same window, and that a depth-3 tree trained on 39 benchmarks transfers to held-out benchmarks.
Editorial extensions
If this is right
- A processor can capture most of the cross-policy adaptation benefit with two L1D prefetchers and a one-bit selector, leaving instruction prefetching and L2 replacement untouched.
- A practical selector does not need to run or emulate the inactive prefetcher: passive demand counters plus a small frozen tree recover 62.4% of the gap, and UCB on executed IPC recovers 73.4%.
- Any counterfactual or introspection hardware that reports what the inactive policy would have done must be near-exact and available within one window; otherwise it performs no better than passive monitoring.
- The two-stage method — measure the full composition space, then reduce candidates by oracle coverage, complementarity, and switching scope — transfers to other policy axes such as branch predictors, replacement rules, or schedulers.
- Modest hysteresis (a two-window minimum residence) cuts switching activity by 36% at a small loss cost, bounding how often prefetcher metadata must be reset and relearned.
Reading between the lines
- An untested extension is to fuse the two practical signals: executed IPC and demand features have different failure modes (stale rewards versus transfer error), so a hybrid selector could plausibly beat both the 0.407% and 0.465% mean losses.
- The 18 phases losing more than 10% mean the binary selector still leaves a tail; a third emergency candidate or a low-confidence fallback to the always-Gaze static choice might recover part of that tail without reopening the full eight-way action space.
- The counterfactual sensitivity numbers give a concrete specification for future introspection hardware: to be worth building, it must deliver a near-exact winner signal with less than one window of latency and no more than a few percent error.
- Because the decision tree is trained on SPEC traces, deployment on other workload classes would need retraining or online threshold adaptation; a direct test is to measure prefix-to-remainder label stability on cloud or HPC traces.
Editorial analysis
A structured set of objections, weighed in public.
Referee Report
Summary. The paper studies interactions among three microarchitectural policy axes (L1D prefetching, L1I prefetching, and L2 replacement), each with two modern candidates, giving eight complete configurations. Using 490 phases from 49 public SPEC CPU2006/SPEC CPU2017 ChampSim traces, it defines the best global static policy (BGSP) by oracle-win frequency, finds that the BGSP (Gaze/Entangling/Mockingjay) loses 1.33% on average to the per-phase oracle while exposing a costly tail, and then argues that the eight-way oracle opportunity compresses to a single binary choice between Berti and Gaze with BARCA/PACIPV fixed, coming within 0.039% aggregate IPC of the full oracle. The paper then evaluates runtime selectors: a UCB rule using executed-policy IPC, a passive demand-stream decision tree, and an idealized counterfactual winner-history signal. The headline results are that UCB recovers 73.4% of the pairwise oracle gap and the demand tree recovers 62.4%, while exact counterfactual winner history gives only a small, delay/error-sensitive improvement.
Significance. If the results hold up, this is a useful contribution to computer architecture. It is, to my knowledge, the first systematic composition study of these modern memory-hierarchy policies, and it makes a credible case that the practical opportunity is concentrated in a one-bit L1D-prefetcher decision rather than in the full eight-way space. The paper is also methodologically serious in several ways: it uses a common ChampSim codebase, public traces, benchmark-disjoint training/test splits for the demand tree, explicit phase/window distinctions, and multiple sensitivity analyses. The counterfactual study in Section V-H is a nice attempt to bound the value of inactive-policy observation, and the negative result for compact confidence signals (Section V-C) is informative. The main weakness is that several load-bearing numbers are obtained through model selection on the same evaluation data, and no confidence intervals are given, so the reported recovery rates are likely optimistic and their precision is unknown. These issues are fixable within the scope of a revision.
major comments (4)
- [V-B, Eq. (4)] The UCB hyperparameters are tuned on the same 4,900-window population used to report the 73.4% recovery. Section V-B states that the reported point uses history length 3 and c=0.03 after sweeping history lengths {3,5,10,20} and c from 0.01 to 0.20. The mean loss of 0.407% is therefore a post-selection estimate, not the loss of a fixed rule on unseen data. Please provide a nested evaluation: tune on a subset of traces (or via cross-validation) and report test performance on untouched traces, with confidence intervals. If the unbiased estimate is materially lower, the claim that UCB 'captures much of the opportunity' needs qualification.
- [V-E and V-F] The demand-tree protocol also selects on the evaluation set. The 20% prefix is chosen because it is 'the best short prefix in this split' (Section V-E), and depth 3 with all six features is selected after observing held-out results (Section V-F). The held-out 1,000 windows are thus reused for both model selection and reporting, so the 0.465% loss and 62.4% recovery are post-selection estimates. Please use a three-way split (train/validation/test) or nested leave-one-benchmark-out selection, and report test performance on traces that never influenced prefix, depth, or feature-set choices. Also report variance across multiple held-out splits.
- [III-D] The Berti/Gaze pair is selected using oracle coverage, complementarity, and switching scope computed over the full 4,900-window set, which includes the ten held-out benchmarks used later for the demand-tree evaluation. This means the 0.039% aggregate-IPC compressibility claim and the pairwise gap for the primary pair are not evaluated on data untouched by the pair choice. Even if the pair-selection criteria are viewed as design choices rather than learned parameters, the transfer claim would be cleaner if pair selection were restricted to the training set or if the authors reported sensitivity of the headline recovery to alternative pairs selected under leave-one-out splits.
- [V, Tables IV and VII] No confidence intervals or per-benchmark error bars are provided for the primary numbers. The key figures (0.407%, 0.465%, 0.320% mean loss; 62.4% and 73.4% recovery; 0.039% compressibility) are point estimates over 4,900 or 1,000 windows from only 49/10 distinct traces. Given that most of the opportunity is concentrated in a few high-loss phases, these estimates may be sensitive to benchmark composition. Please add bootstrap confidence intervals or per-benchmark spread for the main metrics, and state whether the difference between the UCB and demand-tree recovery rates is within noise.
minor comments (5)
- [III-D, footnote 1] The footnote distinguishing 'percentage of raw count' from 'percentage of distinct timesteps' for Figures 3 and 4 is confusing, since 'timesteps' and 'raw count' appear to refer to the same phases. Please clarify exactly how the two figures are computed.
- [V-C, Table III] The 'Best nonlinear model' row reports the same accuracy (50.3%) as raw confidence comparison but a lower mean loss. Please explain why accuracy does not improve despite the lower loss; this is relevant to the text's emphasis on loss over accuracy.
- [V-D] The phrase 'unpruned tree has 15 entries' should say '15 nodes' (7 internal, 8 leaves) for clarity, since 'entries' could be confused with stored thresholds.
- [V-A] The UCB evaluation is on all 4,900 windows while the demand-tree evaluation is on 1,000 held-out windows. This difference is partly acknowledged in Figure 6, but Section V-A should state it explicitly before presenting the 73.4% and 62.4% recovery figures side by side.
- [II-E and throughout] The equations are formatted with inconsistent spacing (e.g., 'IP Coracle(ϕ)' and 'Lossagg (c)'). Please use consistent LaTeX/typographic conventions for variable names and subscripts.
Circularity Check
Headline 62.4–73.4% recovery numbers are post-selection: prefix, depth, and UCB hyperparameters are chosen on the same held-out/evaluation windows used to report them, making the 'predictions' fitted minima; the underlying empirical comparisons are otherwise independent.
-
fitted input called prediction
[Section V-E / V-F (demand-flow tree prefix, feature, and depth selection)]
"Section V-E: 'We select 20% because it is the best short prefix in this split and preserves a substantial post-decision interval.' Section V-F: 'The hardware-friendly point is also the best evaluated point: the complete six-feature vector and at most three comparisons.' Section V-D: 'With a 20% prefix, the demand-flow tree reaches 0.465% mean loss and 72.6% accuracy on the 10 held-out benchmarks.'"
The paper chooses the prefix length, feature set, and tree depth by inspecting held-out performance on the same 10 benchmarks that later produce the headline result. 'Best short prefix in this split' and 'best evaluated point' show that the 20% prefix and depth-3/all-features design are selected by minimizing held-out loss. The reported 0.465% mean loss and 62.4% recovery are therefore the value of the selection objective on the evaluation set, a fitted minimum rather than an independent estimate of transfer. The 'prediction' is statistically forced by the prior look at the test labels.
-
fitted input called prediction
[Section V-B (executed-performance UCB sweep)]
"Section V-B: 'The reported point keeps the three most recent rewards per candidate and uses exploration coefficient c=0.03. We also sweep history lengths of 3, 5, 10, and 20 windows and c from 0.01 to 0.20.' 'Over all 4,900 windows, UCB lowers mean loss from 1.53% for the pair-static always-Gaze baseline to 0.407%, a 3.75× reduction... Therefore, UCB recovers 73.4% of the pairwise-oracle gap...'"
The UCB history length (3) and exploration coefficient (c=0.03) are chosen from a sweep over history lengths 3–20 and c=0.01–0.20. The sweep is evaluated on the same 4,900-window population on which the 0.407% mean loss and 73.4% recovery are then reported. Selecting hyperparameters on the evaluation population and reporting the resulting loss on the same population makes the recovery an in-sample fitted value, not an unbiased measurement of the executed-performance tier. A nested or separate validation set would be needed to treat 73.4% as a prediction.
full rationale
The paper's core measurements are empirical and self-contained: all eight configurations are simulated in the same ChampSim codebase, IPC losses are computed from the measured oracle, and the demand tree is trained on benchmark-disjoint data. The selectors genuinely use only the information they claim. However, the headline generalization numbers are not fully independent. Section V-E selects the 20% prefix because it is the best short prefix in the held-out split, and Section V-F selects depth 3 and the six-feature vector because they are the best evaluated point on the same held-out benchmarks; the reported 0.465% loss / 62.4% recovery is therefore the value of the selection objective on the test set, a fitted minimum rather than an unbiased prediction. Similarly, Section V-B sweeps UCB history length and exploration coefficient on the full 4,900-window population and reports the loss/recovery on that same population. These are post-selection estimates: a nested validation (e.g., choosing hyperparameters on training splits and only then touching the test split) would be needed to support the transfer claim. The Section III-D pair selection also uses oracle coverage on the full 4,900-window set, but the 0.039% compressibility claim is explicitly bounded to those windows, so I treat it as a selection-bias caveat rather than a circular prediction. Self-citations (IPU [16], Sahm [33]) are non-load-bearing: IPU is invoked only to motivate an idealized counterfactual upper bound, which is not claimed as an implementation, and the counterfactual conclusions are derived from the authors' own experiments, not from the citation. Overall: partial circularity in the headline 'prediction' numbers, while the underlying method and pairwise comparisons have independent content.
Assumptions & free parameters
free parameters (6)
- UCB exploration coefficient c =
0.03
- UCB history length =
3 windows
- Decision tree depth =
3
- Sampling prefix fraction =
20% of window
- Decision tree thresholds =
7 internal-node thresholds
- Minimum residence hold =
1 window
assumptions (6)
- domain assumption ChampSim with the specified configuration (Table I) is a faithful model of a real 6-wide out-of-order core and memory hierarchy.
- domain assumption SPEC CPU2006 and SPEC CPU2017 ChampSim traces are representative of general-purpose workloads for evaluating memory system policies.
- domain assumption The eight selected policies are strong, competitive modern policies, so the comparison bounds the realistic opportunity for runtime adaptation.
- domain assumption The demand-stream features are action-independent and can be computed without perturbing the cache hierarchy.
- ad hoc to paper Phase and window lengths (20M and 200K instructions) are appropriate for measuring policy behavior without noise.
- domain assumption For the counterfactual bound, the repeat-last rule using winner history is an upper bound on any predictor of the inactive policy.
invented entities (2)
-
Policy Selector Block (PSB)
-
Ideal counterfactual observer
Cite this review
Pith. "Pith review of Beyond Static Policies: Dynamic Selection Among Modern Microarchitectural Policies." pith.science (2026). https://pith.science/paper/OQQ2FHBB
@misc{pith2026260801038,
author = {Pith},
title = {Pith review of: Beyond Static Policies: Dynamic Selection Among Modern Microarchitectural Policies},
year = {2026},
howpublished = {\url{https://pith.science/paper/OQQ2FHBB}},
note = {Machine review of arXiv:2608.01038}
}
read the original abstract
Modern processors gain performance from interacting policies: prefetchers, predictors, replacement rules, and schedulers. These policies are often evaluated one at a time, yet a policy that wins in one stack may lose in another. To study these effects, we present the first systematic composition study of two L1D prefetchers, two L1I prefetchers, and two L2 replacement policies across 490 phases from 49 SPEC CPU2006 and SPEC CPU 2017 traces. We define the best global static policy (BGSP) by phase-level oracle-win frequency. Gaze/Entangling/Mockingjay is the BGSP, winning 33.47% of phases, yet it remains 1.33% below the phase oracle on average, with 52 phases across eight benchmarks losing more than 2.5%. The opportunity is highly compressible: a Berti/Gaze pair that changes only the L1D prefetcher comes within 0.039% aggregate IPC of the eight-configuration oracle, reducing runtime control to one bit per 200K-instruction window. Given that one-bit interface, we frame selector design as an information problem: what can hardware know before choosing? We evaluate selectors that use only chosen-policy IPC, selectors that passively monitor the demand stream before either prefetcher changes cache state, and an ideal counterfactual observer that exposes the inactive-policy winner signal. The main practical result is that both executed-performance feedback and passive demand monitoring techniques capture much of the two-policy opportunity, recovering 62.4% to 73.4% of the pairwise oracle gap without executing or emulating the inactive prefetcher. The counterfactual study shows that inactive-policy observation must be nearly exact and available within one window to improve on executed-performance or passive demand monitoring. These results suggest a general method for adapting among microarchitectural policies as an additional pathway for processor improvement, distinct from structural resizing.
Figures
Figures from the paper (5 more)
Reference graph
Works this paper leans on
-
[1]
Characterizing machine learning-based runtime prefetcher selection,
E. S. Alcorta, M. Madhav, R. Afoakwa, S. Tetrick, N. J. Yadwadkar, and A. Gerstlauer, “Characterizing machine learning-based runtime prefetcher selection,”IEEE Computer Architecture Letters, vol. 23, no. 2, pp. 146–149, 2024
work page 2024
-
[2]
Lightweight ML-based runtime prefetcher selection on many- core platforms,
E. S. Alcorta, M. Madhav, S. Tetrick, N. J. Yadwadkar, and A. Ger- stlauer, “Lightweight ML-based runtime prefetcher selection on many- core platforms,”arXiv preprint arXiv:2307.08635, 2023
arXiv 2023
-
[3]
Pythia: A customizable hardware prefetching framework using online reinforcement learning,
R. Bera, K. Kanellopoulos, A. Nori, T. Shahroodi, S. Subramoney, and O. Mutlu, “Pythia: A customizable hardware prefetching framework using online reinforcement learning,” inProceedings of the 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021, pp. 1121–1137
work page 2021
-
[4]
Z. Chen, C. Wu, Y . Gu, R. Jia, J. Li, and M. Guo, “Gaze into the pattern: characterizing spatial patterns with internal temporal correlations for hardware prefetching,” in2025 IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE, 2025, pp. 173– 187
work page 2025
-
[5]
Managing multi-configuration hardware via dynamic working set analysis,
A. S. Dhodapkar and J. E. Smith, “Managing multi-configuration hardware via dynamic working set analysis,” inProceedings of the 29th Annual International Symposium on Computer Architecture, 2002, pp. 233–244
work page 2002
-
[6]
Coordinated control of multiple prefetchers in multi-core systems,
E. Ebrahimi, O. Mutlu, C. J. Lee, and Y . N. Patt, “Coordinated control of multiple prefetchers in multi-core systems,” inProceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, 2009, pp. 316–326
work page 2009
-
[7]
G. Gerogiannis and J. Torrellas, “Micro-armed bandit: Lightweight and reusable reinforcement learning for microarchitecture decision-making,” inProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023
work page 2023
-
[8]
The championship simulator: Ar- chitectural simulation for education and competition,
N. Gober, G. Chacon, L. Wang, P. V . Gratz, D. A. Jimenez, E. Teran, S. Pugsley, and J. Kim, “The championship simulator: Ar- chitectural simulation for education and competition,”arXiv preprint arXiv:2210.14324, 2022
arXiv 2022
Show all 34 references
-
[9]
Barca: Branch agnostic region searching algorithm,
D. A. J. P. V . Gratz and G. C. N. Gober, “Barca: Branch agnostic region searching algorithm,”The First Instruction Prefetching Championship, 2020
2020
-
[10]
Learning memory access patterns,
M. Hashemi, K. Swersky, J. Smith, G. Ayers, H. Litz, J. Chang, C. Kozyrakis, and P. Ranganathan, “Learning memory access patterns,” inProceedings of the 35th International Conference on Machine Learn- ing, ser. Proceedings of Machine Learning Research, vol. 80. PMLR, 2018, pp....
2018
-
[11]
Self-optimizing memory controllers: A reinforcement learning approach,
E. Ipek, O. Mutlu, J. F. Mart ´ınez, and R. Caruana, “Self-optimizing memory controllers: A reinforcement learning approach,” inProceedings of the 35th Annual International Symposium on Computer Architecture, 2008, pp. 39–50
2008
-
[12]
Back to the future: Leveraging belady’s algorithm for improved cache replacement,
A. Jain and C. Lin, “Back to the future: Leveraging belady’s algorithm for improved cache replacement,” inProceedings of the 43rd Interna- tional Symposium on Computer Architecture, 2016, pp. 78–89
2016
-
[13]
High perfor- mance cache replacement using re-reference interval prediction (rrip),
A. Jaleel, K. B. Theobald, S. C. Steely Jr, and J. Emer, “High perfor- mance cache replacement using re-reference interval prediction (rrip),” ACM SIGARCH computer architecture news, vol. 38, no. 3, pp. 60–71, 2010
2010
-
[14]
Dynamic branch prediction with percep- trons,
D. A. Jim ´enez and C. Lin, “Dynamic branch prediction with percep- trons,” inProceedings of the Seventh International Symposium on High- Performance Computer Architecture, 2001, pp. 197–206
2001
-
[15]
Learning-based phase-aware multi- core cpu workload forecasting,
E. S. A. Lozano and A. Gerstlauer, “Learning-based phase-aware multi- core cpu workload forecasting,”ACM transactions on design automation of electronic systems, vol. 28, no. 2, pp. 1–27, 2022
2022
-
[16]
IPU: Flexible hardware introspection units,
I. McDougall, S. Wadle, H. Batchu, and K. Sankaralingam, “IPU: Flexible hardware introspection units,” inProceedings of the 53rd Annual International Symposium on Computer Architecture, ser. ISCA ’26. New York, NY , USA: Association for Computing Machinery, 2026
2026
-
[17]
Combining branch predictors,
S. McFarling, “Combining branch predictors,” Digital Equipment Cor- poration Western Research Laboratory, Tech. Rep. TN-36, 1993
1993
-
[18]
Best-offset hardware prefetching,
P. Michaud, “Best-offset hardware prefetching,” inProceedings of the 22nd International Symposium on High Performance Computer Archi- tecture, 2016, pp. 469–480
2016
-
[19]
A survey of techniques for dynamic branch prediction,
S. Mittal, “A survey of techniques for dynamic branch prediction,” Concurrency and Computation: Practice and Experience, vol. 31, no. 1, p. e4666, 2019
2019
-
[20]
Light-weight cache replacement for instruction heavy workloads,
S. Mostofi, S. Gupta, A. Hassani, K. Tibrewala, E. Teran, P. V . Gratz, and D. A. Jim ´enez, “Light-weight cache replacement for instruction heavy workloads,” inProceedings of the 52nd Annual International Symposium on Computer Architecture, 2025, pp. 1005–1019
2025
-
[21]
Berti: an accurate local-delta data prefetcher,
A. Navarro-Torres, B. Panda, J. Alastruey-Bened ´e, P. Ib´a˜nez, V . Vi˜nals- Y´ufera, and A. Ros, “Berti: an accurate local-delta data prefetcher,” in 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, 2022, pp. 975–991
2022
-
[22]
Intelligent adaptation of hardware knobs for improving performance and power consumption,
C. Ortega, L. Alvarez, M. Casas, R. Bertran, A. Buyuktosunoglu, A. E. Eichenberger, P. Bose, and M. Moreto, “Intelligent adaptation of hardware knobs for improving performance and power consumption,” IEEE Transactions on Computers, vol. 70, no. 1, pp. 1–16, 2020
2020
-
[23]
Bouquet of instruction pointers: Instruction pointer classifier-based spatial hardware prefetching,
S. Pakalapati and B. Panda, “Bouquet of instruction pointers: Instruction pointer classifier-based spatial hardware prefetching,” inProceedings of the 47th Annual International Symposium on Computer Architecture, 2020, pp. 118–131
2020
-
[24]
Sandbox prefetching: Safe run-time evaluation of aggressive prefetchers,
S. H. Pugsley, Z. Chishti, C. Wilkerson, P.-f. Chuang, R. L. Scott, A. Jaleel, S.-L. Lu, K. Chow, and R. Balasubramonian, “Sandbox prefetching: Safe run-time evaluation of aggressive prefetchers,” in Proceedings of the 20th International Symposium on High Performance Computer ...
2014
-
[25]
Adaptive insertion policies for high performance caching,
M. K. Qureshi, A. Jaleel, Y . N. Patt, S. C. Steely Jr., and J. S. Emer, “Adaptive insertion policies for high performance caching,” in Proceedings of the 34th Annual International Symposium on Computer Architecture, 2007, pp. 381–391
2007
-
[26]
Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches,
M. K. Qureshi and Y . N. Patt, “Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches,” inProceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, 2006, pp. 423–432
2006
-
[27]
A cost-effective entangling prefetcher for instructions,
A. Ros and A. Jimborean, “A cost-effective entangling prefetcher for instructions,” in2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA). IEEE, 2021, pp. 99–111
2021
-
[28]
Effective mimicry of belady’s min policy,
I. Shah, A. Jain, and C. Lin, “Effective mimicry of belady’s min policy,” in2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA). IEEE, 2022, pp. 558–572
2022
-
[29]
Automatically characterizing large scale program behavior,
T. Sherwood, E. Perelman, G. Hamerly, and B. Calder, “Automatically characterizing large scale program behavior,” inProceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems, 2002, pp. 45–57
2002
-
[30]
Applying deep learning to the cache replacement problem,
Z. Shi, X. Huang, A. Jain, and C. Lin, “Applying deep learning to the cache replacement problem,” inProceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019, pp. 413–425
2019
-
[31]
A hierarchical neural model of data prefetching,
Z. Shi, A. Jain, K. Swersky, M. Hashemi, P. Ranganathan, and C. Lin, “A hierarchical neural model of data prefetching,” inProceedings of the 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021, pp. 861–873
2021
-
[32]
Feedback directed prefetching: Improving the performance and bandwidth-efficiency of hardware prefetchers,
S. Srinath, O. Mutlu, H. Kim, and Y . N. Patt, “Feedback directed prefetching: Improving the performance and bandwidth-efficiency of hardware prefetchers,” inProceedings of the 13th International Sym- posium on High Performance Computer Architecture, 2007, pp. 63–74
2007
-
[33]
Sahm: State-aware heterogeneous mul- ticore for single-thread performance,
S. Wadle and K. Sankaralingam, “Sahm: State-aware heterogeneous mul- ticore for single-thread performance,”arXiv preprint arXiv:2509.22405, 2025
2025
-
[34]
Attention, distillation, and tabularization: Towards practical neural network-based prefetching,
P. Zhang, N. Gupta, R. Kannan, and V . K. Prasanna, “Attention, distillation, and tabularization: Towards practical neural network-based prefetching,”arXiv preprint arXiv:2401.06362, 2024
2024 arXiv
Reviewed August 6, 2026 · model on record in the stance chip above.
Discussion (0). Sign in to comment.