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ForgeEDA: A Comprehensive Multimodal Dataset for Advancing EDA

T0 review · 3 major / 7 minor · reviewed 2026-08-16 · deepseek-v4-flash

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Pith's one-line read A new open dataset of 1,189 chip designs provides 83,155 logic graphs and shows more training data improves AI for EDA.

desk verdict A useful multimodal EDA dataset whose AI scaling claims are undercut by the lack of a documented held-out evaluation split. read the letter →

arxiv 2505.02016 v1 pith:PDM5LBUU submitted 2025-05-04 cs.AR

Zhengyuan Shi , Zeju Li , Chengyu Ma , Yunhao Zhou , Ziyang Zheng , Jiawei Liu , Hongyang Pan , Lingfeng Zhou
show 14 more authors
Kezhi Li Jiaying Zhu Lingwei Yan Zhiqiang He Chenhao Xue Wentao Jiang Fan Yang Guangyu Sun Xiaoyan Yang Gang Chen Chuan Shi Zhufei Chu Jun Yang Qiang Xu
This is my paper · ORCID
classification cs.AR
keywords ForgeEDAopen-sourcedatasetlogicsynthesisAIforcircuitrepresentationlearningpowerperformanceareaAnd-InverterGraphsdatascaling
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper introduces ForgeEDA, a large open-source multimodal dataset for electronic design automation (EDA). It collects 1,189 Verilog repository designs spanning processors, AI accelerators, arithmetic units, encoders/decoders, interfaces, and controllers, then runs synthesis and physical design flows to produce 4,450 post-mapping netlists, 4,450 placed netlists, and 4,450 And-Inverter Graphs, plus 83,155 sub-graphs for model training. The authors argue that existing open EDA datasets are too small or too narrow, and that their dataset's scale and diversity let researchers benchmark synthesis tools and train circuit-learning models more fairly. On benchmarks, open-source synthesis tools fall behind commercial tools by about 1.77x in area and 1.20x in delay on average, and graph-neural-network models for circuit learning improve steadily as training data grows from 1% to the full dataset. The paper's central claim is that this public infrastructure will close the data gap that has slowed AI for EDA.

What carries the argument

The central object is the dataset itself, with its four linked circuit representations: RTL source code, post-mapping netlists, placed netlists, and And-Inverter Graphs, along with 83,155 randomly extracted sub-AIGs of 500-5,000 nodes stored as graph representations for PyTorch Geometric. The mechanism that makes it useful is the explicit alignment of all formats and their accompanying synthesis, placement, and timing reports to a single design, so the same circuit can be studied at each stage of the EDA flow. This alignment supports both benchmarking of EDA tools on identical input/output pairs and supervised training of circuit-learning models on graph structure plus PPA labels.

What would settle it

A concrete check is to retrain a circuit model on a matched set of full-chip synthesized netlists: if the data-scaling gains seen on ForgeEDA's module-level sub-AIGs disappear, the module-as-top-level shortcut is not a valid proxy for real design diversity.

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Extended reading notes

Core claim

ForgeEDA is a multimodal circuit dataset that binds four representations of each design into one resource: RTL source code, post-mapping netlists, placed netlists with physical-design reports, and And-Inverter Graphs. The construction expands coverage by collecting repositories via datasheet-derived keywords and by synthesizing each module as a separate top module, turning 1,189 repositories into 4,450 netlists. The paper evaluates the dataset in two ways: it benchmarks logic synthesis and AIG optimization, exposing a substantial performance gap between open-source and commercial tools, and it trains representative circuit-learning models on the graphs, showing that model error decreases monotonically as the training subset grows from 1% to 10% to the full dataset. The conclusion is that the scale and diversity of training data are decisive for AI4EDA and that ForgeEDA supplies the missing resource.

Load-bearing premise

The dataset's comprehensiveness rests on the assumption that the 1,189 synthesizable Verilog repositories collected from the internet via datasheet keywords are representative of real-world chip design diversity, while treating each module as a separate top module assumes module-level synthesis statistics are meaningful proxies for full-chip PPA.

Editorial extensions

If this is right

  • Researchers can use ForgeEDA's 4,450 netlists and 83,155 sub-AIGs to train and evaluate circuit representation models, with evidence that larger training subsets lower prediction error.
  • Logic-synthesis benchmarking is no longer confined to near-saturated small benchmarks; the dataset reveals that open-source synthesis tools lag commercial tools by roughly 1.77x in area and 1.20x in delay on average.
  • The multimodal alignment lets users study how design decisions propagate across synthesis and physical design stages, including timing reports extracted after placement.
  • Public release gives researchers a common ground for comparing PPA prediction and logic-optimization methods, potentially exposing where academic tools fail on real-world designs.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Because each module is synthesized separately as a top module, the netlists are mostly block-level rather than full-system; gains from training on sub-AIGs may not transfer to whole-chip netlists, and a full-chip companion set would be a natural extension.
  • The monotone data-scaling curves invite a formal study of scaling laws for circuit representation learning, potentially predicting how much data a target error requires.
  • All PPA reports come from one 130nm process design kit, so models trained on them may need fine-tuning to transfer to other process nodes or FPGA mappings.
  • The paired RTL code and PPA labels could support fine-tuning large language models to generate synthesizable RTL that is aware of downstream area and delay, an application the paper does not explore.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 7 minor

Summary. ForgeEDA is a proposed open-source multimodal circuit dataset. It collects 1,189 Verilog repositories from the internet based on datasheet-derived keywords, filters them for synthesizability, and synthesizes each module as a top module with Synopsys Design Compiler and the SkyWater 130nm PDK, producing 4,450 post-mapping netlists, 4,450 placed netlists, 4,450 AIGs, and 83,155 sub-AIGs with PPA and timing reports. The paper benchmarks DCU against Yosys on RTL synthesis, compares several ABC synthesis and mapping scripts, and trains five GNN models on two tasks (gate probability prediction and equivalent gate identification), reporting lower MAE as training data size increases. The central claims are that ForgeEDA exposes performance gaps among EDA tools and improves AI4EDA performance and generalization through scale and diversity.

Significance. If the dataset is released as described and the evaluation issues are fixed, ForgeEDA would be a valuable contribution. Its multi-representation coverage across RTL, post-mapping netlists, placed designs, and AIGs is broader than OpenABC-D or CircuitNet, and the scale (83,155 sub-AIGs) is substantially larger than existing public corpora. The resource could support benchmarking and pre-training for circuit representation learning. The use of standard EDA tools and the concrete generation pipeline are strengths. However, the significance is conditional on the evidence for generalization, which is currently not established because the training/evaluation protocol in Section V is underspecified.

major comments (3)
  1. [Section V.A.2, Tables IV and V] Tables IV and V are central to the claim that ForgeEDA improves generalization, but the evaluation protocol is not described. Section V.A.2 says only that 'we further divide our training dataset into 10% and 1% subsets'; it does not state whether the reported MAE values are computed on training or held-out data, nor the unit of the split. Because Section III.B.3 states that sub-AIGs are 'randomly extracted' from 4,450 parent AIGs, a split at the sub-AIG level can place sub-circuits of the same parent design in both training and test, leaking structural information and inflating scaling gains. The authors must specify a test split that is disjoint at the repository or AIG level, and must report held-out test MAE alongside training MAE.
  2. [Section IV.A, Table III] Table III's geomean and 'Imp.' rows are not internally consistent. The DCU geomean (48,523.05 µm², 14,604.15 ps) is computed over all 20 rows, whereas the Yosys geomean (71,987.59 µm², 15,944.40 ps) is computed over only the 16 benchmarks that Yosys completes, since four cells contain '–'. Moreover, the ratios of these geomeans are 71,987.59/48,523.05 ≈ 1.48 for area and 15,944.40/14,604.15 ≈ 1.09 for delay, not the reported 1.77× and 1.20×. The text should state exactly how 'Imp.' was computed, for example as a geomean of per-benchmark ratios over the 16 common benchmarks, and the numbers should be recalculated; as written, the performance-gap claim in Section IV.A is not reproducible.
  3. [Section III.B] The claim that ForgeEDA reflects 'real-world' chip design diversity is not yet supported by the reported construction. Section III.B.1 describes keyword-based repository collection and synthesizability filtering, but gives no provenance statistics, deduplication procedure, size distribution, or license documentation; Section III.B.2 then treats each module as a separate top module during synthesis. Consequently, modules from one repository become independent samples and the reported PPA statistics are module-level, not full-chip values. The paper should either provide quantitative evidence that the collection spans realistic complexity and diversity, such as gate counts, design hierarchy, and category balance, and explicitly discuss the module-as-top simplification as a limitation, or it should temper the 'comprehensive' and 'real-world' claims.
minor comments (7)
  1. [Section II.A] Section II.A says ForgeEDA covers '7 categories and 22 sub-categories of circuit designs,' but the Abstract, Introduction, Table I, and Conclusion all state 6 categories and 20 divisions; these counts should be reconciled.
  2. [Table I] Table I has a typo: 'Multipiler' should be 'Multiplier'; the affiliation list also spells 'Intergrated' for 'Integrated.'
  3. [Section IV.A] The text says 'we employed a variety of advanced open-source tools and commercial EDA solutions,' but the experiment compares only DCU and Yosys; the wording should match the actual scope.
  4. [Figures 2 and 3] Figures 2 and 3 do not define 'area reduction' and 'delay reduction' or report the per-benchmark values underlying the geometric-mean markers; definitions and raw data should be supplied.
  5. [Section V] The GNN experiments do not report hyperparameters, training epochs, random seeds, or model sizes, which are necessary for reproducing Tables IV and V.
  6. [Dataset Availability] No URL or release mechanism for the dataset is given; for an open-source dataset paper, a download link and usage instructions should be provided.
  7. [Tables IV and V] The column labels 'Loss Value' should say 'MAE' to match the equations and the text, which define the metric as mean absolute error.

Circularity Check

1 steps flagged · score 6.0 of 10

Data-scaling results in Tables IV/V are training-loss comparisons; the abstract's generalization claim is not independently tested.

  1. fitted input called prediction [Section V.A.2 (Experiment Setting) and V.A.3 (Result Analysis), Tables IV and V; also Eqs. (2) and (4)]
    "We further divide our training dataset into 10% and 1% subsets to evaluate the data scalability of the models and assess the effectiveness of our expanded dataset. Table IV summarizes the performance results, where lower MAE indicates better performance."

    The reported quantity in Tables IV/V is called 'loss value' and is computed by Eqs. (2)/(4) as MAE between the model prediction and the ground-truth label. The experiment section only describes subsets of 'our training dataset' and never defines a held-out test set, split unit, or evaluation split. On the present text, the table entries are therefore the training loss itself—the same objective minimized during training. Under that reading, the monotone decrease in loss from 1% to 10% to full dataset is expected by construction: a model trained on more of the scored examples fits them better, so the claimed 'as dataset size increases, MAE decreases ...

full rationale

The dataset construction and the practical EDA evaluations are externally grounded: RTL collection is from internet repositories, synthesis uses Synopsys DCU and Skywater 130nm PDK, placement uses Cadence Innovus, and AIG generation/STA uses ABC. The Yosys-vs-DCU and AIG-optimization comparisons do not reduce to the paper's own definitions or fitted parameters, so those parts are self-contained. The self-citations to DeepGate2, PolarGate, and DeepGate3 are used as baselines or background motivation; they are not the load-bearing evidence for the central claim once the AI4EDA evaluation is examined. The circularity is confined to the data-scaling demonstration in Tables IV/V: with no test split described, the reported MAE is the training objective, so the observed improvement with dataset size is a fitting artifact rather than evidence of generalization. This makes the abstract's 'improve model performance and generalization' claim partially circular, warranting a score of 6 rather than a higher score, because the dataset itself and the tool benchmarks retain independent content.

Assumptions & free parameters 0 free parameters · 3 assumptions · 0 invented entities

The paper introduces no fitted parameters and no invented entities. Its central claims rest on data-collection and preprocessing assumptions about representativeness and granularity, listed above.

assumptions (3)
  • domain assumption The 1,189 Verilog repositories gathered from the internet using datasheet keywords and filtered for synthesizability are representative of real-world chip designs.
    Section III.B.1. If the collection is skewed toward small educational modules or duplicates, the claims of comprehensiveness and real-world coverage weaken, and the data-scaling gains shown in Section V may not transfer to full-chip designs.
  • domain assumption Treating each module as the top module in synthesis produces PPA metrics and netlists that are meaningful for benchmarking and training.
    Section III.B.2. This expands 1,189 repositories to 4,450 netlists but changes design granularity; the effect of module-level versus full-chip data is never discussed.
  • domain assumption Randomly extracted sub-AIGs of 500 to 5,000 nodes are adequate training samples for circuit representation learning.
    Section III.B.3. Subsampling may change functional and structural distributions; the paper provides no analysis of whether sub-AIGs preserve the characteristics of full designs.

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Cite this review

Pith. "Pith review of ForgeEDA: A Comprehensive Multimodal Dataset for Advancing EDA." pith.science (2026). https://pith.science/paper/PDM5LBUU

@misc{pith2026250502016,
  author       = {Pith},
  title        = {Pith review of: ForgeEDA: A Comprehensive Multimodal Dataset for Advancing EDA},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/PDM5LBUU}},
  note         = {Machine review of arXiv:2505.02016}
}
read the original abstract

We introduce ForgeEDA, an open-source comprehensive circuit dataset across various categories. ForgeEDA includes diverse circuit representations such as Register Transfer Level (RTL) code, Post-mapping (PM) netlists, And-Inverter Graphs (AIGs), and placed netlists, enabling comprehensive analysis and development. We demonstrate ForgeEDA's utility by benchmarking state-of-the-art EDA algorithms on critical tasks such as Power, Performance, and Area (PPA) optimization, highlighting its ability to expose performance gaps and drive advancements. Additionally, ForgeEDA's scale and diversity facilitate the training of AI models for EDA tasks, demonstrating its potential to improve model performance and generalization. By addressing limitations in existing datasets, ForgeEDA aims to catalyze breakthroughs in modern IC design and support the next generation of innovations in EDA.

Figures

Figures reproduced from arXiv: 2505.02016 by the authors.

Figure 1
Figure 1. Overview of ForgeEDA [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. AIG Optimization Results performs the worst, indicating limitations in its generalization ability for the various benchmarks. C. AIG Technology Mapping We used the optimized AIG as input to generate mapped netlists and evaluated the mapping efficiency based on netlist area and delay. As illustrated in [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 3
Figure 3. AIG Technology Mapping Results TABLE IV COMPARISON OF LOSS VALUE FOR PROBABILITY PREDICTION ACROSS DIFFERENT DATASET SPLITS Model Full Dataset 10% Dataset 1% Dataset GCN [44] 0.0683 0.1661 0.2497 GAT [45] 0.1579 0.3470 0.3775 GraphSAGE [46] 0.0307 0.0596 0.2199 DeepGate2 [27] 0.0335 0.0466 0.1965 PolarGate [42] 0.0148 0.0164 0.0192 existing circuit learning models and assess their effectiveness, including probabilit… view at source ↗

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Forward citations

Cited by 3 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. Miter-Aware LUT Mapping: Aligning Structure and Solvability for Efficient Logic Equivalence Checking

    cs.AR 2026-07 conditional novelty 6.0 of 10

    Joint LUT mapping of golden and implementation circuits, combined with Gaussian-guided XOR modeling and solver-oriented LUT selection, reduces SAT-based logic equivalence checking runtime by up to 92.1%.

  2. TRACE: Learning to Compute on Circuit Graphs

    cs.AI 2025-09 conditional novelty 6.0 of 10

    A per-operator hierarchical Transformer with a residual function shift objective substantially improves learning functional behavior of circuit graphs.

  3. DeepCell: Self-Supervised Multiview Fusion for Circuit Representation Learning

    cs.LG 2025-02 conditional novelty 6.0 of 10

    DeepCell fuses AIG and post-mapping netlist views with masked autoencoding, achieving 2.77% lower ECO patch cost and 15-16% lower area-delay product in technology mapping.

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Pith tools

Reviewed August 16, 2026 · model on record in the stance chip above.