Mamba-X: An End-to-End Vision Mamba Accelerator for Edge Computing Devices

Dongho Yoon; Dongjae Lee; Gungyu Lee; Jaewon Chang; Minsoo Rhu; Yunjae Lee

REVIEW 3 major objections 5 minor 76 references

Mamba-X: An End-to-End Vision Mamba Accelerator for Edge Computing Devices

T0 review · 3 major / 5 minor · reviewed 2026-08-06 · deepseek-v4-flash

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Pith's one-line read The paper claims a purpose-built systolic scan array can make Vision Mamba's selective-scan bottleneck 11.6x faster on edge hardware, yielding a 2.3x end-to-end speedup.

desk verdict A coherent edge-vision-Mamba accelerator with a genuinely new scan-array idea, but the headline speedups rest on an unvalidated simulator. read the letter →

arxiv 2508.02977 v1 pith:PG3IHXLP submitted 2025-08-05 cs.AR

Dongho Yoon , Gungyu Lee , Jaewon Chang , Yunjae Lee , Dongjae Lee , Minsoo Rhu This is my paper

classification cs.AR

keywords VisionMambastatespacemodelsselectivescansystolicarrayacceleratoredgeinferencepost-trainingquantizationKogge-Stonealgorithmenergyefficiency

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper tries to establish that the sequential selective-scan operation inside Vision Mamba, not the matrix multiplications, is what makes the model slow on edge GPUs, and that a purpose-built systolic array can remove that bottleneck. Mamba-X is claimed to deliver an average 11.6x selective-scan throughput gain, a 2.3x end-to-end speedup, an 11.5x energy-efficiency improvement, and a 601x performance-per-area gain compared with a 30W edge GPU, while keeping top-1 accuracy loss below one percentage point on ImageNet-1K. The authors' central insight is that the Kogge-Stone parallel prefix recurrence can be refactored into a systolic dataflow in which scan elements communicate only with their neighbours, avoiding the shared-memory spills and branch divergence that hurt GPU-based scans. If true, the work would make high-resolution Vision Mamba inference practical on resource-constrained devices.

What carries the argument

The load-bearing object is the Systolic Scan Array (SSA), a grid of Scan Processing Elements (SPEs), each with two multipliers and an adder, that implements the Kogge-Stone recurrence steps $P_n P_{n+1}$ and $P_{n+1} Q_n + Q_{n+1}$ while passing partial results only to neighbouring SPEs. This local, rhythmic dataflow eliminates explicit shared-memory writes of intermediate states and runs different state dimensions as independent parallel rows. The Long Input Support Unit (LISU) stitches partial states across sequence chunks, and the hybrid quantization scheme makes the required rescaling a shift rather than a multiplication; a 16-32 entry LUT-based SFU handles SiLU, exponential, and softplus.

What would settle it

Build the Mamba-X RTL described in Section 5 at the stated 65nm target, run the Tiny/Small/Base Vision Mamba models on an FPGA or test chip at 224 to 1024 resolutions, and measure end-to-end latency, energy, and ImageNet-1K top-1 accuracy; if selective-scan throughput is materially below 11.6x or accuracy loss exceeds about 1 percentage point, the central claim fails.

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Extended reading notes

Core claim

Mamba-X's central claim is that a dedicated accelerator can make Vision Mamba practical on edge devices by targeting the selective SSM block. On a conventional edge GPU the paper finds the selective SSM consumes up to 60% of encoder latency for high-resolution inputs, because fused scan kernels limit parallelism along the state dimension and because small on-chip SRAM forces intermediate state vectors to spill off-chip. Mamba-X counters both problems with a systolic scan array that scans chunks of the sequence across state dimensions in parallel, a Long Input Support Unit that threads partial state between chunks, and an INT8 hybrid quantization scheme that rounds scaling factors to powers of two so rescaling becomes shift operations. The result, as the authors state it, is that scan throughput rises 11.6x, end-to-end latency falls 2.3x, energy efficiency rises 11.5x, and performance per area rises 601x while accuracy loss stays under 1%p.

Load-bearing premise

The load-bearing premise is in Section 5: Mamba-X is modeled as a cycle-level C++ simulator, and only area comes from synthesized RTL; if the simulator's cycle counts, power, or memory traffic are optimistic, the 11.6x, 11.5x, and 601x results would not transfer to real hardware.

Editorial extensions

If this is right

If the reported figures hold, the selective scan stops being a serial bottleneck, so Vision Mamba can be deployed at higher resolutions on edge hardware without retraining the model.
The hybrid INT8 quantization with power-of-two rescaling means the scan-path hardware needs only integer adders, multipliers, and shifters, reducing per-operation energy and on-chip buffer pressure.
A $1.34\,\mathrm{mm}^2$ footprint scaled to 12nm (0.4% of the baseline GPU die) suggests the SSA and GEMM engine could be reused as a small IP block inside a larger edge SoC.
The speedup is largest where the selective SSM dominates, so the reported gains should grow with input resolution from 224 to 1024, consistent with the paper's breakdown.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

The same systolic scan dataflow should extend to Mamba-style language models, whose selective recurrence is identical; that is an extrapolation the paper does not make.
The power-of-two rounding of activation scaling factors is a robustness bet: a deployment distribution with different outliers than the 500 calibration images could push the accuracy loss above the reported margin, a test the paper does not perform.
The 601x performance-per-area figure assumes the simulator's throughput and the RTL-synthesized area combine without DRAM scheduling, clocking, or integration overheads, so real-system numbers may be lower.
The characterization suggests the accelerator's advantage narrows as model size grows and GEMMs dominate, pointing to a future co-design where the GEMM engine also receives attention.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Short version: Mamba-X has a genuine architectural idea—refactoring Mamba’s Kogge-Stone selective scan into a systolic array with inter-chunk chaining—and the paper’s characterization of Vision Mamba on a Jetson-class GPU is well done. The headline speedup and energy numbers, however, rest entirely on a C++ cycle-level simulator that is never validated against the RTL the authors also synthesized. Treat the quantitative claims as promising but unproven, and treat the SSA/LISU design as the contribution worth taking seriously.

What is new: combining a systolic scan array with LISU inter-chunk state passing is a legitimate new system design. The profile-guided LUT SFU and the hybrid/channel-wise INT8 quantization are not new individually, but the integration with a shift-based rescaling approximation is thoughtfully done. The area estimate from RTL synthesis and CACTI gives the architecture more concreteness than many accelerator papers. The bottleneck analysis (selective SSM dominating at high resolution, off-chip spilling on Xavier) is useful and reproducible.

Soft spots in proportion: the biggest one is the one the stress-test flags. Energy is computed as synthesized power times simulator cycle time, so any optimism in the simulator’s timing flows directly into the 11.5x energy and 601x performance/area claims. The paper does not describe how SSA cycle counts are derived, how LISU schedules across SSA instances, or whether DRAM refresh and bank conflicts are modeled. That is a validation gap, not a demonstrated error, but it is load-bearing. Second, the accuracy evaluation calibrates quantization scales and SFU breakpoints on 500 images drawn from the same ImageNet-1K test set used for reporting accuracy. That is mild test-set leakage and should be fixed or acknowledged. Third, the abstract’s “without sacrificing accuracy” does not match Table 5, which shows 0.6–0.9 point top-1 losses. Those losses are small and arguably acceptable, but the wording should be toned down. Finally, there is no quantitative comparison against MARCA or other SSM accelerators; the related-work discussion says they target different points, which is fair, but a side-by-side would help.

Who should read it: computer architects working on edge SSM and vision accelerators, and anyone building on Mamba-family models for low-power inference. I would send it to peer review rather than desk-reject; the design deserves a serious referee, but the referee should be asked to scrutinize the simulator and demand either validation or a clearly labeled uncertainty analysis. I would cite it for the architecture idea, not for the speedup numbers.

Referee Report

3 major / 5 minor

Summary. The paper proposes Mamba-X, an end-to-end accelerator for Vision Mamba inference on edge devices. The architecture combines a systolic scan array (SSA) for the selective scan operation, a long-input support unit (LISU) for inter-chunk dependencies, a LUT-based special function unit (SFU), and a hybrid channel/tensor-granularity INT8 quantization scheme with power-of-two scaling-factor approximation. The authors characterize Vision Mamba on an NVIDIA Jetson AGX Xavier, identify the selective SSM as the main bottleneck, and report that Mamba-X achieves an average 11.6x improvement in selective scan throughput, an average 11.5x end-to-end energy-efficiency improvement, a 601x increase in average performance/area, and under 1 percentage point top-1 accuracy loss on ImageNet-1K.

Significance. If the reported results hold, Mamba-X would be a useful contribution to edge inference for state-space vision models: the characterization of the GPU bottleneck is concrete, the SSA/LISU design is a plausible architectural response to the sequential scan dependency, and the quantization-aware SPE design is well motivated. The area estimate is grounded in RTL synthesis, which is a strength relative to purely analytical proposals. However, the central performance, energy, and area-efficiency numbers are produced by a cycle-level simulator that is not validated against RTL simulation or hardware, and the accuracy evaluation uses a calibration set drawn from the same ImageNet-1K test set on which accuracy is reported. These issues are load-bearing for the paper's headline claims.

major comments (3)

[Section 5 (Performance) and Section 6.1] All speedup, energy-efficiency, and performance/area claims (11.6x, 11.5x, and 601x in Sections 1 and 6) rest on a cycle-level C++ simulator that is not validated against the synthesized RTL or any hardware prototype. Section 5 states that only area is estimated from RTL synthesis (Table 4), while energy is computed by multiplying RTL-synthesized power by the simulator's inference time. The manuscript does not specify how SSA or LISU cycle counts are derived, how DRAM refresh or bank conflicts are modeled, or whether the Jetson baseline is modeled at achieved throughput. Because any systematic timing optimism propagates directly into the energy-efficiency and performance/area results, please validate the simulator against RTL or measured hardware for at least one configuration, and provide a sensitivity analysis of the headline results to the main timing assumptions.
[Section 4.4 and Section 6.3, Table 5] The accuracy evaluation is circular. Section 4.4 states that quantization scaling factors are calibrated using 500 randomly sampled images from the 50,000-image ImageNet-1K test set, and Section 6.3 reports final top-1/top-5 accuracy on that same dataset. Since the calibration images are part of the evaluation set, the reported 0.59-0.89 percentage-point accuracy losses in Table 5 are likely optimistic. Please calibrate on a disjoint set (for example, a held-out portion of the training split) and report accuracy excluding any calibration images, or quantify the degree to which the 500-image calibration set inflates the reported accuracies.
[Tables 4-5 and Figures 17-18] The accuracy claim of 'under 1 percentage point degradation' is established only at 224x224 resolution, whereas the performance, energy, and area-efficiency claims are reported across 224, 512, 738, and 1024 resolutions. Quantization ranges, SFU breakpoint selection, and LISU inter-chunk behavior all interact with sequence length, so the accuracy result does not automatically transfer to the higher resolutions featured in the performance evaluation. Please measure accuracy at higher resolutions or explicitly qualify the accuracy claim to 224x224.

minor comments (5)

[Table 1] Table 1 does not state which model size is used; the baseline accuracy of 76.04% matches the Tiny model in Table 5, so please label the table accordingly.
[Section 6.2] The 601x performance/area improvement is reported without a precise definition; please state whether it is the ratio of normalized inverse latencies divided by area, and describe how the technology scaling from 65 nm to 12 nm is applied to the comparison with the 12 nm Jetson AGX Xavier.
[Section 5 (Energy)] The energy model uses a fixed 4 pJ/bit for LPDDR4 off-chip transfers; please clarify whether the same value is applied to both the baseline GPU and Mamba-X, and whether DRAM refresh overhead is included in either model.
[Equation (1)] The rounding notation in Equation (1) is not defined; please state explicitly that X_q is obtained by round-to-nearest with ties handled in a particular way, as the quantization results are sensitive to this choice.
[Figure 8] The term 'oracular ideal GPU design' is informal; consider replacing it with a more precise description such as 'an infinite-capacity on-chip storage baseline'.

Circularity Check

1 steps flagged · score 4.0 of 10

Accuracy claims are partially circular because quantization scale factors are calibrated on a subset of the ImageNet-1K test set and then evaluated on that same test set; hardware speedup/energy claims are simulator-based but not circular.

fitted input called prediction [Section 4.4 (Hybrid quantization) and Section 5 (Model accuracy); Table 5]
"We observe that using only 1% of the test dataset (500 randomly sampled images from the 50,000-image ImageNet-1K dataset) provides a robust estimation of global maximum and minimum values for configuring our scaling factors. ... When measuring model accuracy, we use the ImageNet-1K [8] dataset, which contains 50,000 images at a resolution of 224 x 224."

The quantization scaling factors s from Equation (1) are fitted to 500 images drawn from the ImageNet-1K test set, and Table 5 reports top-1/top-5 accuracy on the full ImageNet-1K test set, which includes those same 500 images. The reported less-than-1%p accuracy loss is therefore not an independent prediction on unseen data; the quantization parameters were tuned to the evaluation set, so the accuracy result is partially forced by the calibration. This is a fitted-input-called-prediction pattern: the fitted scale factors are reused in the accuracy evaluation on the same test instances.

full rationale

The central hardware claims (11.6x selective-scan throughput, 2.3x end-to-end speedup, 11.5x energy-efficiency, 601x performance/area) are produced by a cycle-level simulator and RTL-based area/power estimation; they do not reduce to fitted parameters or to self-citation. The main circularity is confined to the accuracy evaluation: the paper explicitly calibrates scale factors using 1% of the ImageNet-1K test set and then evaluates accuracy on that same test set. This is a real methodological leakage that partially invalidates the reported accuracy as an independent prediction, but it does not by construction force the hardware efficiency numbers. Because the central hardware derivation is independent and the accuracy circularity affects only one component of the paper's claims, a moderate score of 4 is appropriate rather than a higher score reserved for fully circular derivations.

Assumptions & free parameters 6 free parameters · 6 assumptions · 3 invented entities

These are the premises Mamba-X's reported numbers rest on beyond the architecture description itself. Most are standard algorithmic facts or domain assumptions for SSM inference, but the simulator fidelity, the process-scaling methodology, and the test-set calibration are load-bearing and not independently verified.

free parameters (6)

Number of SSA instances = 8 (with 1, 2, 4 also shown)
Table 2 sets the headline configuration to 8 SSAs. No optimization procedure is given, and the speedup scales directly with this count.
Chunk size = 16
Table 2 sets chunk size to 16. This determines LISU inter-chunk behavior and the reported parallel speedup, but the paper gives no sensitivity analysis or method for choosing 16.
GEMM engine size = 64x64 PEs
Table 2 fixes the GEMM engine at 64x64 PEs. Area, energy, and end-to-end speedup all depend on this manually selected design point.
SFU LUT sizes and breakpoints = 16 entries for exponential, 32 for SiLU and softplus
LUT sizes are chosen from Figure 19, and the breakpoints and linear coefficients are fitted by gradient descent within ranges profiled from ImageNet inference. These are data-fitted parameters.
Activation and weight scaling factors for INT8 quantization = Derived from 500 ImageNet calibration images
Equation 1 defines scale factors from global max/min values. The paper estimates these from 1% of the ImageNet test set, and the accuracy results in Table 5 depend on these fitted values.
SPE fixed-point intermediate precision = 2 extra fractional bits
Section 4.2 states intermediate values use 2 extra fractional bits to maintain accuracy. No sensitivity study is reported for this precision choice.

assumptions (6)

standard math Kogge-Stone parallel prefix algorithm is a correct inclusive-scan formulation for the selective SSM recurrence.
The SSA dataflow in Section 4.2 relies on the Kogge-Stone algorithm from Section 3.2 to compute states in O(log^2 N) steps.
domain assumption Zero-order hold discretization of the continuous-time SSM is the correct model for Vision Mamba.
Section 2.1 presents the discrete SSM using zero-order hold discretization following Gu and Dao. The accelerator computes on this discretized form.
ad hoc to paper The cycle-level C++ simulator faithfully models Mamba-X and the edge GPU baseline.
Section 5 says performance is modeled with a C++ cycle-level simulator. No validation against RTL simulation or measured hardware is presented, yet all speedup and energy-efficiency claims rely on this fidelity.
domain assumption Scaling 65nm synthesized area and energy to 12nm using the equations of Stillmaker and Baas is accurate for this design.
Section 5 describes scaling the synthesized 65nm design to 32nm and then comparing to the 12nm Jetson. The scaling methodology is standard but introduces uncertainty.
ad hoc to paper The 500-image calibration set sampled from the ImageNet-1K test set is representative and does not inflate the reported accuracies.
Section 4.4 uses 1% of the test dataset to estimate activation maxima and minima. The accuracy numbers in Section 6.3 are measured on the same benchmark, so the calibration step is not a fully held-out procedure.
domain assumption The CUB-based fused selective SSM kernel is a representative state-of-the-art implementation on the edge GPU baseline.
Section 3.2 attributes the baseline GPU implementation to NVIDIA CUB and Vision Mamba's open-source kernel. If the baseline is suboptimal, the reported speedups would be inflated.

invented entities (3)

Systolic Scan Array (SSA)
purpose: Executes selective scan in parallel by passing partial states directly between neighboring Scan Processing Elements, avoiding explicit on-chip memory round trips.
The SSA is described and evaluated only through the authors' cycle-level simulator and RTL synthesis. No fabricated chip, FPGA prototype, or external benchmark verifies its behavior.
Scan Processing Element (SPE)
purpose: Dual-multiplier unit that computes P_{n+1}Q_n + Q_{n+1} and P_n P_{n+1} concurrently for the systolic scan dataflow.
The SPE is a new microarchitectural component of Mamba-X. Its timing and area come from the authors' RTL synthesis, not from independent hardware validation.
Long Input Support Unit (LISU)
purpose: An additional row of SPEs in the PPU that chains partial states across chunk boundaries so multiple SSAs can process chunks in parallel.
LISU is introduced to solve the inter-chunk dependency problem. Its correctness is illustrated by diagrams and assumed in the simulator, without independent evidence.

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Cite this review

Pith. "Pith review of Mamba-X: An End-to-End Vision Mamba Accelerator for Edge Computing Devices." pith.science (2026). https://pith.science/paper/PG3IHXLP

@misc{pith2026250802977,
  author       = {Pith},
  title        = {Pith review of: Mamba-X: An End-to-End Vision Mamba Accelerator for Edge Computing Devices},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/PG3IHXLP}},
  note         = {Machine review of arXiv:2508.02977}
}

abstract

Transformers have proven effective in language modeling but are limited by high computational and memory demands that grow quadratically with input sequence length. State space models (SSMs) offer a promising alternative by reducing attention complexity from $O(L^2)$ to $O(L)$ while also lowering overall memory consumption. Vision Mamba adapts the SSM approach for computer vision tasks, achieving lower latency and memory consumption than traditional transformer models. However, deploying Vision Mamba on edge devices is challenging due to its sequential scan operations, which hinder GPU efficiency. We propose Mamba-X, an end-to-end Vision Mamba accelerator that includes a systolic scan array to maximize parallelism and minimize memory traffic, along with a hybrid, hardware-friendly quantization technique to reduce memory usage and improve hardware efficiency without sacrificing accuracy.

Figures

Figures reproduced from arXiv: 2508.02977 by the authors.

**Figure 1.** Comparison of (a) end-to-end latency and (b) memory consumption when the Vision Transformer (ViT) [10] and Vision Mamba are executed on NVIDIA’s Jetson AGX Xavier. As depicted, the advantages of Vision Mamba in terms of compute (latency) and memory efficiency grow as the input image size increases. known to incur high memory consumption in conventional attention-based transformer architectures, making Mamba well-sui… view at source ↗

**Figure 2.** SSM in (a) continuous and (b) discrete time domain. computed based on the input sequence 𝑢𝑛. This enables the model to identify the most relevant input information. Overall, Mamba has proven effective in language modeling as it reduces the computational complexity of the attention mechanism from 𝑂(𝐿 2 ) to 𝑂(𝐿) (𝐿: input sequence length). By eliminating the need to store the score matrix and key-value cache, both … view at source ↗

**Figure 3.** (a) Vision Mamba architecture, which substitutes ViT’s transformer-based encoders with Vision Mamba encoders. (b) An overview of the selective SSM block. The selective SSM block used in the forward/backward paths of (a) are identical to the selective SSM shown in (b). ΔA and ΔB · 𝑢 are first computed using element-wise multiplication (Step ❶). The selective scan operation is then performed, which executes across t… view at source ↗

Figures from the paper (14 more)

**Figure 4.** Figure 4: Vision Mamba’s latency breakdown based on key operations in its encoder block. For images larger than 512×512, selective SSM accounts for up to 60% of total latency across all models. and 𝑋𝑓 , 𝑋𝑞 are the original floating-point and quantized values, respectively. Deq…

**Figure 6.** Figure 6: (a) Illustration of how the selective scan operation can better leverage parallelism by adopting the Kogge-Stone algorithm where at each step, the result (𝑐𝑏 + 𝑑) is used to compute the state. (b) Execution flow showing selective scan computations across the warps with…

**Figure 7.** Figure 7: Roofline analysis of the selective SSM and GEMM in Vision Mamba on NVIDIA Jetson AGX Xavier. Selective SSM is executed on the CUDA Core, while GEMM is executed on the Tensor Core, unless the cuBLAS runtime opts in on the CUDA core option for better performance (e.g., 5…

**Figure 8.** Figure 8: Off-chip memory traffic of the selective SSM on NVIDIA A100 and Jetson AGX Xavier, measured using NVIDIA Nsight Compute [49]. All data points are normalized to Ideal’s READ when the input image is 224×224. along the L dimension. The warp-level results are then stored …

**Figure 10.** Figure 10: Dataflow of selective SSM in Mamba-X. projection operations, (3) a vector processing unit (VPU) conducting all vector operations (e.g., LayerNorm, Conv1D, flip or element-wise operations), (4) a special function unit (SFU) performing non-linear operations within the …

**Figure 12.** Figure 12: Comparison of how the selective scan operation for the three rows of Δ𝐴 and Δ𝐵 · 𝑢 in [PITH_FULL_IMAGE:figures/full_fig_p007_12.png]

**Figure 13.** Figure 13: assumes a scenario where three SSAs are instantiated and the workloads are divided into three chunks, with each chunk assigned to a different SSA. The input chunks are fed into the arrays at one-cycle intervals to facilitate seamless execution and efficient scheduli…

**Figure 14.** Figure 14: (a) Example of how SiLU function can be approximated using linear interpolation. (b) Mamba-X’s profile-guided SFU with a 16-entry LUT. The SFU locates the segment in which each value in the input vector 𝑥 is located, fetches the relevant coefficients from the LUT, and…

**Figure 15.** Figure 15: Magnitude of (a) the weights in the input linear projection layer in the Vision Mamba Encoder (Step ○3 in [PITH_FULL_IMAGE:figures/full_fig_p008_15.png]

**Figure 16.** Figure 16: (a) Histogram of Δ𝐴 scaling factor for backward SSM. (b) The rescaling process is changed from expensive multiplication to relatively cheaper shift operation with hardware-friendly scaling factor approximation [PITH_FULL_IMAGE:figures/full_fig_p009_16.png]

**Figure 18.** Figure 18: The normalized end-to-end (a) latency breakdown and (b) energy-efficiency of Mamba-X compared to the edge GPU. performance improvements and speedups, aided by the LISU within the PPU for efficient inter-SSA communication. In terms of energy-efficiency, Mamba-X signifi…

**Figure 17.** Figure 17: The (a) speedup, (b) energy-efficiency, and (c) off-chip memory traffic during selective SSM block’s execution with MambaX. All results are normalized to the edge GPU system. while the energy consumed by the off-chip memory is calculated by multiplying the number of…

**Figure 19.** Figure 19: Changes in accuracy as the number of LUT entries is varied for the (a) exponential, (b) SiLU, and (c) softplus functions. 72 74 76 78 80 82 Vanilla+H+S+L Vanilla+H+S Vanilla+H Vanilla Vanilla+H+S+L Vanilla+H+S Vanilla+H Vanilla Vanilla+H+S+L Vanilla+H+S Vanilla+H Vani…

**Figure 20.** Figure 20: Top-1 accuracy when the baseline Vision Mamba model (Vanilla) is applied with hybrid quantization (H), hardware-friendly approximation of scaling factors (S), and LUT-based SFU (L). scaling factors being precomputed from a limited calibration set from ImageNet-1K, lea…

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