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REVIEW 2 major objections 5 minor 45 references

RISC-V Word-Size Modular Instructions for Residue Number Systems

T0 review · 2 major / 5 minor · reviewed 2026-08-12 · deepseek-v4-flash

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Pith's one-line read This paper claims that adding word-size mulmod, addmod, and submod instructions to RISC-V makes software RNS modular multiplication up to 2.76x faster in-order and 3.06x out-of-order than pseudo-Mersenne moduli, and 4.5x to 8x faster than…

desk verdict Solid simulation study, but the headline speedups depend on unvalidated 2/4-cycle latencies for the custom modular instructions. read the letter →

arxiv 2412.05286 v1 pith:PM2SYPUN submitted 2024-11-21 cs.AR cs.DC

Laurent-Stéphane Didier (IMATH) , Jean-Marc Robert (IMATH) This is my paper · ORCID
classification cs.ARcs.DC
keywords ResidueNumberSystemsmodularmultiplicationRISC-Vword-sizearithmeticbaseextensionpseudo-Mersennemoduliinstructionsetcycle-levelsimulation
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper tries to show that the main obstacle to software Residue Number Systems (RNS) is the word-size modular reduction, and that RISC-V processors can remove that obstacle by adding three dedicated instructions: mulmod, addmod, and submod, each computing a result modulo a third register in one instruction. On cycle-level simulations of 64-bit In Order and Out of Order processors, the fastest configuration combines these instructions with Kawamura's base extension and beats the best software-only method (pseudo-Mersenne moduli) by a factor of 2.76 in-order and 3.06 out-of-order for 4096-bit modular multiplication. The same simulations show the instruction-equipped RISC-V completing the operation with 4.5 times fewer cycles than x86 in-order and 8 times fewer out-of-order, under matched cache, memory, and frequency settings. If the assumed hardware latencies are realistic, this would make RNS competitive in software on an open ISA, relevant to cryptography and signal processing.

What carries the argument

The load-bearing mechanism is a three-input, one-output instruction format in the RISC-V custom-opcode space: mulmod rd, rs1, rs2, rs3 computes rd = (rs1 × rs2) mod rs3; addmod and submod do the same for addition and subtraction, using the third operand as the modulus. This turns the word-size modular reduction, normally a full division, into a single operation with fixed simulated latency (2 cycles for addmod, 4 for mulmod, or 4/9 in the long-delay case). The evaluation wraps these instructions around Algorithm 1, an RNS Montgomery modular multiplication with base extensions: the first conversion uses the approximate method from [9], and the second uses either Szabo-Tanaka or Kawamura's base extension, the latter estimating the CRT quotient k with O(n) word-size operations.

What would settle it

Measure a real 64-bit RISC-V implementation of mulmod/addmod/submod and rerun the 64-channel Kawamura-base-extension software: if the actual latencies approach or exceed the long-delay case (9 and 4 cycles) or force a pipeline stall for the extra register operand, the 2.76x/3.06x advantages over pseudo-Mersenne will not reproduce. A cheaper test is to re-run the same simulations with mulmod delay set above 9 cycles and addmod above 4 and observe the crossover point where pseudo-Mersenne wins.

Watch

Extended reading notes

Core claim

The paper's central claim is that dedicated word-size modular arithmetic instructions change which RNS algorithm is best. With such instructions, the fastest implementation is RNS Montgomery modular multiplication that uses an approximate first base extension and Kawamura's approximate-quotient base extension for the second conversion: for 64 channels (4096-bit moduli) it runs in about 135,700 cycles in-order and 43,900 cycles out-of-order on the simulated RISC-V, versus about 342,400 and 134,100 cycles for pseudo-Mersenne moduli with the same base extension. The speedups are 2.76x and 3.06x, and the instruction version beats the simulated x86 baseline by 4.5x in-order and 8x out-of-order. The gain survives longer operator delays: with mulmod at 9 cycles and addmod at 4, the instruction version is still about 1.9x to 2.7x faster than pseudo-Mersenne in the configurations tested.

Load-bearing premise

The entire comparison rests on the assumption that the new instructions can be implemented with the simulated latencies—4 cycles for mulmod and 2 for addmod—and that the four-operand encoding costs no extra pipeline delays; the paper acknowledges these delays could be longer in a real implementation.

Editorial extensions

If this is right

  • On an in-order RISC-V core, the instruction-based implementation with Kawamura's base extension is 2.76x faster than the fastest pseudo-Mersenne implementation, making it the best configuration among those compared.
  • Out-of-order cores extract more from the instructions, reaching 3.06x, because independent RNS channels can issue in parallel.
  • Even if the modular units are slow (mulmod 9 cycles, addmod 4), the instruction version remains about 1.9x faster in-order and 2.3x to 2.7x faster out-of-order than pseudo-Mersenne reduction.
  • Against x86 with the same memory hierarchy and frequency, the simulated RISC-V with the new instructions needs 4.5x fewer cycles in-order and 8x fewer out-of-order for the 64-channel case.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The paper does not quantify end-to-end cryptographic workloads, only the modular-multiplication kernel; applying the same instructions to the surrounding RNS conversions could shift the overall speedup for full RSA or ECC computations.
  • A real four-operand instruction needs an extra register-read port on the pipeline; if that port lengthens the cycle time or adds bypass delays, the cycle-count ratios shrink even though the instruction counts stay the same. A three-operand variant (e.g., reusing rd as the modulus) is a testable alternative the authors list as future work.
  • Because the gain is largest out-of-order, the results suggest RNS-friendly custom instructions are most valuable on superscalar RISC-V cores, and that a vector version of mulmod/addmod would let several RNS channels reduce simultaneously—an extension the paper plans but does not simulate.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

2 major / 5 minor

Summary. The paper proposes three custom RISC-V instructions (addmod, submod, mulmod) for word-size modular arithmetic and evaluates their impact on sequential software implementations of RNS modular multiplication using the GEM5 simulator. It compares three word-size modulo methods (C compiled modulo, pseudo-Mersenne reduction, custom instructions) and two base-extension algorithms (Szabo-Tanaka and Kawamura) across in-order (Minor) and out-of-order (O3) models and channel counts from 8 to 64. The headline results are a 2.76x (in-order) and 3.06x (out-of-order) cycle-time speedup of the custom-instruction version over the best software-only implementation (pseudo-Mersenne with Kawamura base extension) and a 4.5x/8x advantage over x86, with a long-delay sensitivity case (mulmod=9, addmod=4) reducing those ratios to 1.92x/2.30x.

Significance. The paper addresses a real bottleneck in software RNS implementations and proposes a concrete, well-scoped ISA extension. Its strengths are the large simulation matrix, the inclusion of a long-delay sensitivity case, and the honest statement that the delays are assumed, not measured. If the assumed latencies are representative, the results strongly motivate future hardware support for word-size modular instructions. However, the central quantitative claims rest on unvalidated microarchitectural assumptions, and the paper does not model the full cost of the four-operand encoding or of a fused multiply-and-reduce datapath. The study is a useful simulation exploration, but the headline speedups should be treated as upper-bound estimates rather than validated performance.

major comments (2)
  1. [§4.4, §5.4, and Abstract] The assumed latencies (mulmod=4, addmod=2; long-delay variant 9 and 4) are load-bearing for the headline speedups. As the paper itself notes in §5.4, 'they could be much longer in a real implementations.' The long-delay case in Table 1 shows the in-order speedup over pseudo-Mersenne falling from 2.76 to 1.92 and the out-of-order from 3.06 to 2.30. The manuscript does not model the extra pipeline costs of the four-operand encoding, such as an additional register-file read port, wider bypass network, or possible issue-width restrictions, and it does not provide a microarchitectural sketch of how a 64-bit multiply-and-reduce modulo an arbitrary runtime modulus could be completed in 4 cycles. Please add a more thorough sensitivity analysis, including a break-even latency, and qualify the abstract's numbers with the long-delay results or an explicit statement that the latency figures are optimistic assumptions.
  2. [§4.1–§4.4] The manuscript does not describe how the custom instructions were integrated into GEM5. It mentions adding them to gcc and checking with Spike, but no details are given about the GEM5 ISA description changes, execution unit configuration, and the timing model for the four-operand format. Without this information, the simulation results are not reproducible. Please include the relevant GEM5 modifications or provide a link to an artifact repository, so that the reported cycle counts can be independently verified.
minor comments (5)
  1. [§4.3] The description of the 'Modulo' baseline is ambiguous. The text says 'In case of processors without DIV instruction, i.e. our situation,' but it does not clarify whether the simulated RISC-V core implements the M extension. If DIV/REM is available, the C modulo operation would use a single REM instruction, which would make the large speedups over 'Modulo' harder to interpret. Please state the exact RISC-V ISA extensions enabled in the simulation.
  2. [§5.3] There is a typo in §5.3: 'Kaxamura' should be 'Kawamura'.
  3. [§5.2 and §5.3] The cross-references to 'Table 2' appear before the table is presented, and the table numbering is confusing because the first table in the text is also called 'Table 1.' Please renumber or restructure the table references for clarity.
  4. [Abstract and §5.4] The abstract says '8 less' cycles; this should be '8 times fewer cycles.' In §5.4, 'in a real implementations' is a grammatical error.
  5. [Figure 1] Figure 1, showing the proposed instruction encodings, is difficult to read because the field boundaries and bit labels are small. A table or a more detailed figure with each field clearly labeled would improve readability.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the speedups are simulation measurements comparing newly proposed instructions against independent baselines, with instruction latencies stated as assumptions rather than fitted to the results.

full rationale

The paper's central claims are empirical GEM5 simulation ratios between RNS modular multiplication using proposed mulmod/addmod instructions and baseline software reductions (C modulo and pseudo-Mersenne moduli). The baseline pseudo-Mersenne reduction is an independent algorithm from Plantard's work, and the RNS algorithm variants (Szabo-Tanaka and Kawamura base extensions) are standard external methods. The instruction latencies (mulmod=4, addmod=2, with a long-delay variant of 9 and 4) are openly declared simulation parameters, not quantities fitted to make the claimed speedups come out; the paper also reports the reduced speedups in the long-delay case, so the result is not defined by its input. Reuse of the authors' earlier RNS library and evaluation protocol [14] provides tooling, not the conclusion, and no load-bearing step reduces by construction to a self-citation or to the measured outputs. The only substantive weakness is that the assumed instruction delays may not hold in real hardware, which is a correctness/risk concern, not circularity.

Assumptions & free parameters 3 free parameters · 3 assumptions · 1 invented entities

The central claim rests on two classes of assumptions: the algorithmic correctness of RNS base extension methods (standard, from prior literature) and the feasibility of the proposed instruction latencies, which are hand-chosen and not validated on hardware. The new instructions are invented entities with no independent evidence beyond the paper's own simulation.

free parameters (3)
  • mulmod instruction latency = 4 cycles (default), 9 (long-delay case)
    Chosen by hand as the assumed execution delay of the proposed modular multiply instruction; not measured from hardware. The headline speedups change materially when this is set to 9.
  • addmod instruction latency = 2 cycles (default), 4 (long-delay case)
    Chosen by hand as the assumed execution delay of the proposed modular add instruction; not measured from hardware.
  • integer multiplier delay = 3 to 4 cycles
    Simulator parameter for the baseline integer multiplier, varied in experiments; affects cycle counts but is less central to the instruction comparison.
assumptions (3)
  • standard math Correctness of the RNS base extension and Montgomery multiplication algorithms.
    The algorithms are taken from prior literature (Kawamura et al., Szabo-Tanaka, Bajard-Imbert) and assumed correct.
  • domain assumption GEM5 simulator faithfully models the performance of the underlying processor and the proposed instructions.
    The paper relies on GEM5's Minor and O3 models to produce cycle counts; validation is cited from other papers, but the custom instruction timing is a modeled parameter, not validated silicon.
  • ad hoc to paper The proposed 4-operand instruction encoding can be implemented without additional pipeline costs beyond the stated ALU latencies.
    The instruction format uses rs3; the paper does not model extra register-read ports or decode/issue overhead, assuming these are negligible.
invented entities (1)
  • addmod, submod, mulmod custom RISC-V instructions
    purpose: Compute word-size modular addition, subtraction, and multiplication in a single instruction to accelerate RNS operations.
    The instructions exist only in a modified GEM5 model and GCC toolchain; the paper provides a functional simulation and Spike check but no hardware implementation or independent benchmark on real silicon.

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Cite this review

Pith. "Pith review of RISC-V Word-Size Modular Instructions for Residue Number Systems." pith.science (2026). https://pith.science/paper/PM2SYPUN

@misc{pith2026241205286,
  author       = {Pith},
  title        = {Pith review of: RISC-V Word-Size Modular Instructions for Residue Number Systems},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/PM2SYPUN}},
  note         = {Machine review of arXiv:2412.05286}
}
read the original abstract

Residue Number Systems (RNS) are parallel number systems that allow the computation on large numbers. They are used in high performance digital signal processing devices and cryptographic applications. However, the rigidity of instruction set architectures of the market-dominant microprocessors limits the use of such number systems in software applications. This article presents the impact of word-size modular arithmetic specific RISC-V instructions on the software implementation of Residue Number Systems. We evaluate this impact on several RNS modular multiplication sequential algorithms. We observe that the fastest implementation uses the Kawamura et. al. base extension. Simulations of architectures with GEM5 simulator show that RNS modular multiplication with Kawamura's base extension is 2.76 times faster using specific word-size modular arithmetic instructions than pseudo-Mersenne moduli for In Order processors. It is more than 3 times for Out of Order processors. Compared to x86 architectures, RISC-V simulations show that using specific instructions requires 4.5 times less cycles in In Order processors and 8 less in Out of Order ones.

Figures

Figures reproduced from arXiv: 2412.05286 by the authors.

Figure 1
Figure 1. The instructions format for word-size modular arithmetic [PITH_FULL_IMAGE:figures/full_fig_p005_1.png] view at source ↗
Figure 2
Figure 2. Intrinsic C function for word-size modular addition [PITH_FULL_IMAGE:figures/full_fig_p006_2.png] view at source ↗
Figure 3
Figure 3. RNS modular multiplication timing in clock cycle number, with In Order [PITH_FULL_IMAGE:figures/full_fig_p010_3.png] view at source ↗
Figures from the paper (3 more)
Figure 4
Figure 4. Figure 4: RNS modular multiplication Speed-Up, comparison of Kawamura [PITH_FULL_IMAGE:figures/full_fig_p011_4.png]
Figure 5
Figure 5. Figure 5: RNS modular multiplication Speed-Up of Inst. over the C modulo oper [PITH_FULL_IMAGE:figures/full_fig_p013_5.png]
Figure 6
Figure 6. Figure 6: RNS modular multiplication Speed-Up of Inst. over the Pseudo-Mersenne [PITH_FULL_IMAGE:figures/full_fig_p015_6.png]

Discussion (0). Continue with ORCID to comment.

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Pith tools

Reviewed August 12, 2026 · model on record in the stance chip above.