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Towards Neural Path Tracing in SRAM

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arxiv 2305.20061 v1 pith:PVCNWMZS submitted 2023-05-31 cs.GR

classification cs.GR
keywords pathneuraltracingscenariossoftwarealreadyanalysingarchitecture
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We present an experimental neural path tracer designed to exploit the large on-chip memory of Graphcore intelligence-processing-units (IPUs). This open source renderer demonstrates how to map path tracing to the novel software and hardware architecture and is a useful tool for analysing in-cache neural-rendering scenarios. Such scenarios will be increasingly important if rasterisation is replaced by combinations of ray/path tracing, neural-radiance caching, and AI denoising/up-scaling, for which small neural networks are already routinely employed. A detailed description of the implementation also serves as a self-contained resource for more general software design on IPU.

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Cited by 1 Pith paper

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. Rendering 3D Gaussians on a Graph Processor

    cs.GR 2026-07 conditional novelty 7.0 of 10

    3D Gaussian Splatting can be rendered on a DRAM-free, locally-connected processor with a NEWS-grid routing scheme, though dense scenes expose capacity limits.

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