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REVIEW 3 major objections 6 minor 68 references

A Novel Extensible Simulation Framework for CXL-Enabled Systems

T0 review · 3 major / 6 minor · reviewed 2026-08-12 · deepseek-v4-flash

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Pith's one-line read Open-source simulator models CXL 3.1 features hardware cannot yet test, matching real CXL memory timing within 0.1%–10%.

desk verdict A genuinely useful CXL simulation framework whose headline 0.1–10% accuracy claim is only validated for a simple CXL 2.0 path, leaving the novel CXL 3.1 features (PBR, DCOH) empirically unsupported but worth refereeing. read the letter →

arxiv 2411.08312 v1 pith:SFPVNYGN submitted 2024-11-13 cs.AR

Yuda An (1) , Shushu Yi (1) , Bo Mao (2) , Qiao Li (2) , Mingzhe Zhang (3) , Ke Zhou (4) , Nong Xiao (5) , Guangyu Sun (1
show 11 more authors
6) Xiaolin Wang (1) Yingwei Luo (1) Jie Zhang (1) ((1) Peking University (2) Xiamen University (3) Institute of Information Engineering Chinese Academy of Sciences (4) Wuhan National Laboratory for Optoelectronics of Huazhong University of Science Technology (5) Sun Yat-sen University (6) Beijing Advanced Innovation Center for Integrated Circuits)
This is my paper · ORCID
classification cs.AR
keywords CXLsimulationframeworkport-basedroutingdevice-managedcoherencePCIe6.0full-duplexsnoopfiltermemorypoolingsystemtopologyexplorationcache
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper claims that the CXL 3.1 features that hardware prototypes cannot yet provide can be simulated accurately by a new open-source framework called ESF: port-based routing (forwarding packets by port ID through multi-level switches instead of through a PCIe tree), device-managed coherence (a device-side agent that sends back-invalidation requests without host involvement), and PCIe 6.0 full-duplex transmission. ESF is organized as an interconnect layer that builds a topology graph and routes packets by shortest path, plus a device layer whose switch, bus, and coherency-agent components implement CXL protocol behavior. Validation against a commercial CXL 2.0 memory expander shows idle latency, bandwidth, and loaded-latency errors between 0.1% and 10%, smaller than the errors of remote-NUMA emulation. Using ESF, the paper finds that chain and tree topologies bottleneck at shared bridge routes, that device-side snoop filters see mostly cold misses and favor recent-entry victim selection, and that mixing reads and writes exploits full-duplex buses to raise bandwidth. If the accuracy holds, researchers can explore CXL 3.1 designs that cannot currently be built or measured.

What carries the argument

The load-bearing mechanism is the two-layer decomposition. The interconnect layer builds a graph of device pairs, assigns every packet a route by shortest path, and hands routing tables to switches; switches then perform port-based routing from any source port to any destination port, which is what permits non-tree topologies and peer-to-peer traffic. The device layer implements protocol behavior: a bus component with per-direction bandwidth allocation models PCIe full-duplex, the DCOH is a fully-associative inclusive snoop filter that allocates entries, sends BISnp requests, and selects victims, and requesters model queues, address interleaving, and cache coherence state. These components communicate only through the interconnect layer, so arbitrary topologies can be assembled and new device types added without changing the routing core.

What would settle it

Compare ESF against a real CXL 3.1 system once one is available: run the same idle-latency, peak-bandwidth, and loaded-latency tests with peer-to-peer traffic through a port-based-routing switch and an enabled device-side coherence agent, and check whether errors stay within the 0.1–10% range. A cheaper check is to measure the added latency of a single back-invalidate snoop on any device-side-coherence hardware and compare it with ESF's predicted snoop-filter path.

Watch

Extended reading notes

Core claim

The central claim is that ESF, built from the ground up rather than patched onto an existing simulator, accurately captures the three features that distinguish CXL 3.1 from earlier versions and from NUMA emulation: 12-bit port-based routing that supports non-tree fabrics, device-managed coherence where a DCOH sends Back-Invalidate Snoop requests without host involvement, and full-duplex PCIe buses that give each direction full bandwidth. The framework routes packets by constructing a topology graph and default shortest-path routing, while individual devices—switches, buses, requesters, memory endpoints, and an inclusive snoop filter—handle protocol functions. The paper reports validation on a real CXL memory expander with errors from 0.1% to 10% for idle latency, peak bandwidth, and loaded-latency curves, and design-space results that expose topology bottlenecks, snoop-filter victim-selection behavior, and the bandwidth benefit of mixing reads and writes.

Load-bearing premise

The load-bearing premise is that timing measurements taken on a CXL 2.0, PCIe 5.0 test machine still apply to the newer CXL 3.1 features ESF adds—switching by port ID, coherence handled by the device side, and the faster PCIe 6.0 link—even though the validation only exercised a simple path from one requester to memory.

Editorial extensions

If this is right

  • Chain and tree topologies cap aggregated bandwidth at the capacity of a single shared switch port, so scaling these topologies adds no performance.
  • Ring topologies provide a second route and roughly double achievable bandwidth; spine-leaf and fully-connected topologies scale further, with fully-connected giving every requester full port bandwidth.
  • Adaptive routing in a spine-leaf fabric substantially improves host bandwidth under noisy-neighbor traffic compared with oblivious routing.
  • A device-side inclusive snoop filter receives mostly cold misses, so LIFO and MRU victim selection outperform FIFO and LRU by about 15% on invalidation count and latency, and a global-frequency policy confirms that FIFO tends to invalidate hot data.
  • Full-duplex PCIe buses turn read-write mixing into a bandwidth win that disappears as header overhead grows, and real workload speedup over half-duplex correlates with the read-write mix degree.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If the latency model transfers to CXL 3.1, peer-to-peer traffic through multi-level PBR switches should show sensitivity to switch-chip latency and routing-table lookup, not just link bandwidth, meaning switch microarchitecture will be a first-order design variable.
  • The snoop-filter results imply that CXL 3.1 memory controllers should treat their DCOH snoop filter as a miss-dominated structure and choose victim selection accordingly; the paper's InvBlk experiments further suggest clearing more than two cachelines per back-invalidation can degrade performance due to cache and bandwidth overhead.
  • The full-duplex finding suggests workload schedulers could deliberately co-locate readers and writers on the same CXL link, since the paper's data indicate roughly a 9% bandwidth gain per 0.1 increase in read-write mix degree.
  • A natural next validation is to test whether the CXL 2.0-calibrated latencies in Table III still hold when port-based routing and device-managed coherence are active; that is the assumption the current validation does not cover.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 6 minor

Summary. The paper presents ESF, a C++ simulation framework for CXL-enabled systems. ESF is organized into an interconnect layer, which builds a topology graph and provides routing information, and a device layer, which models requesters, buses, switches, memory endpoints, and a device-side snoop filter. The framework claims to support CXL 3.1 features including port-based routing (PBR), device-managed coherence (DMC/DCOH) with BISnp/InvBlk commands, and full-duplex PCIe transmission, and it integrates with gem5, DRAMsim3, and SimpleSSD. The authors validate ESF against a real CXL 2.0/PCIe 5.0 memory expander platform, reporting idle latency, peak bandwidth, and loaded-latency errors of 0.1% to 10% and up to 12%, respectively, and they use ESF to explore system topologies, snoop-filter victim-selection policies, InvBlk lengths, and full-duplex effects.

Significance. If the central claims hold, ESF would be a valuable open extensible tool for CXL system research, particularly because it targets CXL 3.1 features that current hardware cannot provide and current simulators do not model. The architectural separation of interconnect and device layers, the support for arbitrary non-tree topologies, and the integrations with gem5, DRAMsim3, and SimpleSSD are genuine strengths, as is the real-hardware validation of the basic CXL.mem path. The paper also gives concrete design-space observations, for example that tree-like topologies create root bottlenecks and that LIFO/MRU victim selection can outperform FIFO/LRU in an inclusive snoop filter. However, the headline claim that ESF 'accurately reflects' the latest CXL 3.1 features is not empirically established by the validation presented, because the validation exercises none of those features.

major comments (3)
  1. [Section IV, Validation] The validation covers only a CXL 2.0/PCIe 5.0 requester-to-memory path: one requester, one bus, and four DRAMsim3 endpoints compared against an MXC-based memory expander. It contains no PBR switch, no DCOH snoop filter, and no PCIe 6.0 link. The paper itself notes in Section II.C that no current hardware prototypes are compatible with CXL 3.1, so the absence of those features from the validation is understandable, but the abstract and conclusion claim that ESF 'accurately reflects' the unique features of the latest CXL protocol and that 'the validation experiment proves the accuracy of ESF.' That claim is broader than the evidence. Please either restrict the accuracy claim to the validated CXL.mem/HDM-H path, or add targeted component-level validation (e.g., microbenchmarks of switch queueing, snoop-filter invalidation flows, or PCIe 6.0 timing from specification-derived models).
  2. [Section IV, Table III] The latency parameters in Table III (requester process time, cache access time, device controller process time, PCIe port delay, bus time, switching time) are calibrated using statistics from the same hardware platform and from prior works, and then the validation metrics are measured on that same platform. As a result, the reported 0.1% to 10% bandwidth errors and up to 12% loaded-latency errors partly measure the quality of the calibration fit rather than independent predictive accuracy. This is a load-bearing issue for the accuracy claim. To address it, provide a sensitivity analysis over the calibrated parameters, or use hold-out validation (for example, validating on a different read-write ratio, request intensity, or endpoint count than the one used for calibration) and report how sensitive the errors are to parameter choices.
  3. [Section V, Design Space Exploration] The quantitative results in Figures 10 through 15 depend on timing values that are not constrained by the validation: the switch latency (20 ns in Table III) and all DCOH/BISnp/snoop-filter timing are unmeasured because the validation path contains no switch and no snoop filter. If the actual switch latency were, say, 60 ns rather than 20 ns, or if a BISnp costs hundreds of cycles rather than tens, the magnitudes of the reported topology bottlenecks, victim-selection effects, and InvBlk effects would change, and the claim that these are accurate reflections of CXL 3.1 behavior would not be supported. Please add a sensitivity analysis over these unvalidated parameters or explicitly present the Section V results as qualitative/illustrative design-space exploration rather than as validated performance predictions.
minor comments (6)
  1. [Abstract and Section II.B] The term 'port-focused routing' is used in the abstract but the rest of the paper uses 'port-based routing (PBR)'; please use one term consistently.
  2. [Section III.D] There are several grammatical errors, e.g., 'We implements a device-side snoop filter' and 'we implements the snoop filter'; these should be corrected.
  3. [Table II] The comparison table is difficult to interpret because the row and column labels are not aligned clearly and empty cells are ambiguous; please add explicit checkmarks or dashes for every framework and feature combination.
  4. [Section IV, Table IV] The text states that ESF shows errors 'as low as 0.7%', but for mcf, gem5-ESF reports 19.8% versus 24.2% on hardware, which is a relative error of about 18%; please report the full error range rather than only the best case.
  5. [Figure 10] The x-axis labels in Figure 10 run together ('ChainTreeRingSLFC'); add spacing or rotate the labels for readability.
  6. [Section III.E] The description of the gem5 integration would benefit from a short data-flow walkthrough of Figure 5a, clarifying how a memory packet passes through UpInterface, the ESF simulation, and DownInterface before returning to gem5.

Circularity Check

1 steps flagged · score 6.0 of 10

Validation accuracy is partly a restatement of the calibration: idle and loaded latencies use Table III latencies fitted to the same CXL MXC hardware, so the reported 0.1%–10% errors are not fully independent.

  1. fitted input called prediction [Section IV (Validation), Table III and Figures 7–8]
    "For calibration, we follow the statistics measured on real hardware platforms and those from multiple prior works [5], [26], [32], [40], [44], [49], [55], and configure the components in ESF with these latency statistics. The detailed configurations are listed in Table III. For validation, we measure three major metrics: idle latency, peak bandwidth under different read-write ratio, and loaded-latency under different request intensity. ... As can be observed, after calibration, ESF exhibits an outstanding latency accuracy compared to NUMA-based emulators using remote DRAM."

    The component latencies in Table III—requester process time 10ns, cache access time 12ns, device controller process time 40ns, PCIe port delay 25ns, bus time 1ns, switching time 20ns—are calibrated using the same CXL MXC/PCIe 5.0 platform on which the validation metrics are later measured with MLC. ESF's idle latency is the sum of these calibrated latencies plus the DRAMsim3 access latency, so matching the hardware idle latency is a direct consequence of the calibration rather than an out-of-sample prediction. The loaded-latency curves (average error 4.3%) inherit the same calibrated parameters.

full rationale

The paper is a simulator-construction paper, and most of its content—PBR switch modeling, DCOH snoop filter, full-duplex bus allocation, gem5/DRAMsim3 wrappers—is independent implementation, not circular. There is no load-bearing self-citation chain and no imported uniqueness theorem. The one genuine circular step is the calibration/validation overlap in Section IV: the latency metrics used as validation are on the same platform whose measured statistics are used to set Table III. The paper even says 'after calibration,' so the circularity is acknowledged in wording, but the abstract's 'validation experiment proves the accuracy' overstates what the experiment can prove. The bandwidth and SPEC CPU2017 overhead comparisons provide some independent support—bandwidth depends on queueing and DRAMsim3, and SPEC overhead is an external workload check—so this is partial circularity rather than a fully forced result. The lack of validation for PBR, DCOH, and PCIe 6.0 is an external-validity gap, not a circularity, and is not counted in the score beyond its effect on the strength of the central accuracy claim.

Assumptions & free parameters 6 free parameters · 4 assumptions · 0 invented entities

The paper introduces a software framework with software components (interconnect layer, device layer, snoop filter, etc.), but no new physical entities. The free parameters are the calibrated latency values that drive the validation results. The axioms are standard domain assumptions plus the questionable assumption that CXL 2.0 validation generalizes to CXL 3.1.

free parameters (6)
  • Requester process time = 10 ns
    Table III: calibrated to match measured hardware latency.
  • Cache access time = 12 ns
    Table III: calibrated to match measured hardware latency.
  • Device controller process time = 40 ns
    Table III: calibrated to match measured hardware latency.
  • PCIe port delay = 25 ns
    Table III: calibrated to match measured hardware latency.
  • Bus time = 1 ns
    Table III: calibrated to match measured hardware latency.
  • Switching time = 20 ns
    Table III: calibrated to match measured hardware latency.
assumptions (4)
  • domain assumption The CXL 3.1 specification accurately describes hardware behavior for port-based routing, device-managed coherence, and PCIe 6.0.
    The paper uses the specification as the basis for all modeling (Section II).
  • domain assumption The latency components in Table III are additive and independent of workload or system scale.
    The validation uses these fixed values for all experiments (Section IV).
  • domain assumption The CXL 2.0 hardware platform used for validation is representative of CXL 3.1 systems.
    The validation platform supports only CXL 2.0 and PCIe 5.0, yet the simulator claims to model CXL 3.1 features (Section IV).
  • domain assumption DRAMsim3 and SimpleSSD provide accurate timing for memory and SSD endpoints.
    The paper integrates these simulators and relies on them for endpoint behavior (Section III-E).

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Cite this review

Pith. "Pith review of A Novel Extensible Simulation Framework for CXL-Enabled Systems." pith.science (2026). https://pith.science/paper/SFPVNYGN

@misc{pith2026241108312,
  author       = {Pith},
  title        = {Pith review of: A Novel Extensible Simulation Framework for CXL-Enabled Systems},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/SFPVNYGN}},
  note         = {Machine review of arXiv:2411.08312}
}
read the original abstract

Compute Express Link (CXL) serves as a rising industry standard, delivering high-speed cache-coherent links to a variety of devices, including host CPUs, computational accelerators, and memory devices. It is designed to promote system scalability, enable peer-to-peer exchanges, and accelerate data transmissions. To achieve these objectives, the most recent CXL protocol has brought forth several innovative features, such as port-focused routing, device-handled coherence, and PCIe 6.0 compatibility. However, due to the limited availability of hardware prototypes and simulators compatible with CXL, earlier CXL research has largely depended on emulating CXL devices using remote NUMA nodes. Unfortunately, these NUMA-based emulators have difficulties in accurately representing the new features due to fundamental differences in hardware and protocols. Moreover, the absence of support for non-tree topology and PCIe links makes it complex to merely adapt existing simulators for CXL simulation. To overcome these problems, we introduce ESF, a simulation framework specifically designed for CXL systems. ESF has been developed to accurately reflect the unique features of the latest CXL protocol from the ground up. It uses a specialized interconnect layer to facilitate connections within a wide range of system topologies and also includes key components to carry out specific functions required by these features. By utilizing ESF, we thoroughly investigate various aspects of CXL systems, including system topology, device-handled coherence, and the effects of PCIe characteristics, leading to important findings that can guide the creation of high-performance CXL systems. The ESF source codes are fully open-source and can be accessed at https://anonymous.4open.science/r/ESF-1CE3.

Figures

Figures reproduced from arXiv: 2411.08312 by the authors.

Figure 2
Figure 2. Hierarchy of CXL Flex Bus layers. Type-1 devices are endpoints with a fully-coherent cache but without a global-visible device local memory. The cache buffers data using the CXL.cache protocol from the host-side memory to utilize the potential data locality. Devices that do not expose their local memory, such as SmartNIC [29], match with type-1. In the root complex, the CXL.cache protocol is mainly served by the coh… view at source ↗
Figure 3
Figure 3. CXL system switching configuration examples. [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figure 4
Figure 4. Overview of the ESF architecture and components. [PITH_FULL_IMAGE:figures/full_fig_p005_4.png] view at source ↗
Figures from the paper (8 more)
Figure 5
Figure 5. Figure 5: Overview of the integration with other simulators. [PITH_FULL_IMAGE:figures/full_fig_p007_5.png]
Figure 7
Figure 7. Figure 7: Idle latency and bandwidth of different platforms. [PITH_FULL_IMAGE:figures/full_fig_p008_7.png]
Figure 9
Figure 9. Figure 9: Examples of different system topologies. [PITH_FULL_IMAGE:figures/full_fig_p009_9.png]
Figure 11
Figure 11. Figure 11: Latency of different system topologies, grouped by [PITH_FULL_IMAGE:figures/full_fig_p010_11.png]
Figure 13
Figure 13. Figure 13: Bandwidth of observed host with different routing [PITH_FULL_IMAGE:figures/full_fig_p010_13.png]
Figure 15
Figure 15. Figure 15: Performance of different InvBlk lengths, normalized to length=1. 0 0 1 /8 1 /4 1 /2 1 0. 0 0. 5 1 . 0 1 . 5 2. 0 N o r m. b a n d wi d t h N ormal i zed h eader overh ead R: W rati o 1 : 0 3: 1 2: 1 1 : 1 1 : 2 1 : 3 0: 1 Half-dupl ex Fu l l -dupl ex [PITH_FULL_IMAGE…
Figure 16
Figure 16. Figure 16: Bandwidth under different R:W ratios and header [PITH_FULL_IMAGE:figures/full_fig_p011_16.png]
Figure 18
Figure 18. Figure 18: Throughput of different real-world traces with differ [PITH_FULL_IMAGE:figures/full_fig_p012_18.png]

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Reference graph

Works this paper leans on

68 extracted references · 62 canonical work pages

  1. [1]

    Ieee standard for ethernet,

    “Ieee standard for ethernet,” https://standards .ieee.org/ieee/802.3/7071/

    work page

  2. [2]

    Nvm express link,

    “Nvm express link,” https://nvmexpress .org/

    work page

  3. [3]

    Serial advanced technology attachment (sata),

    “Serial advanced technology attachment (sata),” https://sata-io .org/

    work page

  4. [4]

    Pci express® 5.0 specification,

    “Pci express® 5.0 specification,” https://pcisig .com/specifications/ pciexpress, 2019

    work page 2019

  5. [5]

    Enabling pcie® 5.0 system level testing and low latency mode for cxl™,

    “Enabling pcie® 5.0 system level testing and low latency mode for cxl™,” https://www.asteralabs.com/videos/aries-smart-retimer-for-pcie- gen-5-and-cxl, 2021

    work page 2021

  6. [6]

    Intel® memory latency checker v3.11,

    “Intel® memory latency checker v3.11,” https://www .intel.com/content/ www/us/en/developer/articles/tool/intelr-memory-latency-checker .html, 2021

    work page 2021

  7. [7]

    Micron® smc 2000 smart memory controllers,

    “Micron® smc 2000 smart memory controllers,” https: //www.microchip.com/en-us/products/memory/smart-memory- controllers, 2022

    work page 2000

  8. [8]

    Pcie express® 6.0 specification,

    “Pcie express® 6.0 specification,” https://pcisig .com/pci-express-6 .0- specification, 2022

    work page 2022

Show all 68 references
  1. [9]

    Cxl® 3.1 specification,

    “Cxl® 3.1 specification,” https://computeexpresslink .org/cxl- specification/, 2023

    2023

  2. [10]

    Cxl® memory expander controller (mxc) m88mx5891,

    “Cxl® memory expander controller (mxc) m88mx5891,” https:// www.montage-tech.com/MXC/M88MX5891, 2023

    2023

  3. [11]

    Intel® compute express link® (cxl) fpga ip,

    “Intel® compute express link® (cxl) fpga ip,” https://www .intel.com/ content/www/us/en/products/details/fpga/intellectual-property/interface- protocols/cxl-ip.html, 2023

    2023

  4. [12]

    Intel® xeon® gold 6416h processor,

    “Intel® xeon® gold 6416h processor,” https://www .intel.com/content/ www/us/en/products/sku/232389/intel-xeon-gold-6416h-processor- 45m-cache-2-20-ghz/specifications .html, 2023

    2023

  5. [13]

    Ddr5 sdram,

    “Ddr5 sdram,” https://www .jedec.org/standards-documents/docs/jesd79- 5c, 2024

    2024

  6. [14]

    Pin - a dynamic binary instrumentation tool,

    “Pin - a dynamic binary instrumentation tool,” https://www .intel.com/ content/www/us/en/developer/articles/tool/pin-a-dynamic-binary- instrumentation-tool.html, 2024

    2024

  7. [15]

    Mitosis: Transparently self-replicating page-tables for large-memory machines,

    R. Achermann, A. Panwar, A. Bhattacharjee, T. Roscoe, and J. Gandhi, “Mitosis: Transparently self-replicating page-tables for large-memory machines,” Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Syste...

    2019

  8. [16]

    Garnet: A detailed on-chip network model inside a full-system simulator,

    N. Agarwal, T. Krishna, L.-S. Peh, and N. K. Jha, “Garnet: A detailed on-chip network model inside a full-system simulator,” 2009 IEEE International Symposium on Performance Analysis of Systems and Software , pp. 33–42, 2009. [Online]. Available: https://api.semanticscholar.or...

    2009

  9. [17]

    Aligns: A processing-in- memory accelerator for dna short read alignment leveraging sot-mram,

    S. Angizi, J.-J. Sun, W. Zhang, and D. Fan, “Aligns: A processing-in- memory accelerator for dna short read alignment leveraging sot-mram,” 2019 56th ACM/IEEE Design Automation Conference (DAC) , pp. 1– 6, 2019. [Online]. Available: https://api .semanticscholar.org/CorpusID: 163164248

    2019

  10. [18]

    Exploiting cxl-based memory for distributed deep learning,

    M. Arif, K. Assogba, M. M. Rafique, and S. S. Vazhkudai, “Exploiting cxl-based memory for distributed deep learning,” Proceedings of the 51st International Conference on Parallel Processing , 2022. [Online]. Available: https://api.semanticscholar.org/CorpusID:255775666

    2022

  11. [19]

    Analyzing cuda workloads using a detailed gpu simulator,

    A. Bakhoda, G. L. Yuan, W. W. L. Fung, H. Wong, and T. M. Aamodt, “Analyzing cuda workloads using a detailed gpu simulator,” 2009 IEEE International Symposium on Performance Analysis of Systems and Software , pp. 163–174, 2009. [Online]. Available: https://api.semanticscholar....

    2009

  12. [20]

    Kite: A family of heterogeneous interposer topologies enabled via accurate interconnect modeling,

    S. Bharadwaj, J. Yin, B. M. Beckmann, and T. Krishna, “Kite: A family of heterogeneous interposer topologies enabled via accurate interconnect modeling,” 2020 57th ACM/IEEE Design Automation Conference (DAC) , pp. 1–6, 2020. [Online]. Available: https: //api.semanticscholar.or...

    2020

  13. [21]

    The gem5 simulator,

    N. Binkert, B. Beckmann, G. Black, S. K. Reinhardt, A. Saidi, A. Basu, J. Hestness, D. R. Hower, T. Krishna, S. Sardashti, R. Sen, K. Sewell, M. Shoaib, N. Vaish, M. D. Hill, and D. A. Wood, “The gem5 simulator,” SIGARCH Comput. Archit. News , vol. 39, no. 2, p. 1–7, aug

  14. [22]

    Language models are few-shot learners,

    T. B. Brown, B. Mann, N. Ryder, M. Subbiah, J. Kaplan, P. Dhariwal, A. Neelakantan, P. Shyam, G. Sastry, A. Askell, S. Agarwal, A. Herbert- V oss, G. Krueger, T. J. Henighan, R. Child, A. Ramesh, D. M. Ziegler, J. Wu, C. Winter, C. Hesse, M. Chen, E. Sigler, M. Litwin, S. Gray...

    2005 arXiv

  15. [23]

    Spec cpu2017: Next- generation compute benchmark,

    J. Bucek, K.-D. Lange, and J. von Kistowski, “Spec cpu2017: Next- generation compute benchmark,” Companion of the 2018 ACM/SPEC International Conference on Performance Engineering , 2018. [Online]. Available: https://api.semanticscholar.org/CorpusID:4714535

    2018

  16. [24]

    A dna read alignment accelerator based on computational ram,

    Z. I. Chowdhury, M. Zabihi, S. K. Khatamifard, Z. Zhao, S. Resch, M. Razaviyayn, J. Wang, S. S. Sapatnekar, and U. R. Karpuzcu, “A dna read alignment accelerator based on computational ram,” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits , vol. 6, p...

    2020

  17. [25]

    Benchmarking cloud serving systems with ycsb,

    B. F. Cooper, A. Silberstein, E. Tam, R. Ramakrishnan, and R. Sears, “Benchmarking cloud serving systems with ycsb,” in ACM Symposium on Cloud Computing , 2010. [Online]. Available: https://api.semanticscholar.org/CorpusID:2589691

    2010

  18. [26]

    Cxl™ use-cases driving the need for low latency performance retimers,

    T. Do, “Cxl™ use-cases driving the need for low latency performance retimers,” https://www .microchip.com/en-us/about/media-center/blog/ 2020/cxl-use-cases-driving-need-for-low-latency-performance-retimer, 2020

    2020

  19. [27]

    Shortest path,

    W. Fagen-Ulmschneider, “Shortest path,” in Encyclopedia of Algorithms,

  20. [28]

    Liblinear: A library for large linear classification,

    R.-E. Fan, K.-W. Chang, C.-J. Hsieh, X.-R. Wang, and C.-J. Lin, “Liblinear: A library for large linear classification,” Journal of machine learning research, vol. 9, no. Aug, pp. 1871–1874, 2008

    2008

  21. [29]

    Azure accelerated networking: Smartnics in the public cloud,

    D. Firestone, A. Putnam, S. Mundkur, D. Chiou, A. Dabagh, M. Andrewartha, H. Angepat, V . Bhanu, A. M. Caulfield, E. S. Chung, H. K. Chandrappa, S. Chaturmohta, M. Humphrey, J. Lavier, N. Lam, F. Liu, K. Ovtcharov, J. Padhye, G. Popuri, S. Raindel, T. Sapre, M. Shaw, G. Silva,...

    2018

  22. [30]

    Thirty years of regional climate modeling: Where are we and where are we going next?

    F. Giorgi, “Thirty years of regional climate modeling: Where are we and where are we going next?” Journal of Geophysical Research: Atmospheres, vol. 124, pp. 5696 – 5723, 2019. [Online]. Available: https://api.semanticscholar.org/CorpusID:182261868

    2019

  23. [31]

    Amber*: Enabling precise full-system simulation with detailed modeling of all ssd resources,

    D. Gouk, M. Kwon, J. Zhang, S. Koh, W. Choi, N. S. Kim, M. T. Kandemir, and M. Jung, “Amber*: Enabling precise full-system simulation with detailed modeling of all ssd resources,” 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 469–481, 2018...

    2018

  24. [32]

    Direct access, high- performance memory disaggregation with directcxl,

    D. Gouk, S. Lee, M. Kwon, and M. Jung, “Direct access, high- performance memory disaggregation with directcxl,” in USENIX Annual Technical Conference , 2022. [Online]. Available: https: //api.semanticscholar.org/CorpusID:268076421

    2022

  25. [33]

    Simulating dram controllers for future system architecture exploration,

    A. Hansson, N. Agarwal, A. Kolli, T. Wenisch, and A. N. Udipi, “Simulating dram controllers for future system architecture exploration,” in 2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) , 2014, pp. 201–210

    2014

  26. [34]

    Bandwidth-effective dram cache for gpu s with storage-class memory,

    J.-I. Hong, S. Cho, G. Park, W. Yang, Y .-H. Gong, and G. T. Kim, “Bandwidth-effective dram cache for gpu s with storage-class memory,” 2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA), pp. 139–155, 2024. [Online]. Available: https://api.seman...

    2024

  27. [35]

    A detailed and flexible cycle-accurate network-on-chip simulator,

    N. Jiang, D. U. Becker, G. Michelogiannakis, J. D. Balfour, B. Towles, D. E. Shaw, J. Kim, and W. J. Dally, “A detailed and flexible cycle-accurate network-on-chip simulator,” 2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) , pp. 86–9...

    2013

  28. [36]

    Hello bytes, bye blocks: Pcie storage meets compute express link for memory expansion (cxl-ssd),

    M. Jung, “Hello bytes, bye blocks: Pcie storage meets compute express link for memory expansion (cxl-ssd),” Proceedings of the 14th ACM Workshop on Hot Topics in Storage and File Systems , 2022. [Online]. Available: https://api.semanticscholar.org/CorpusID:249960254

    2022

  29. [37]

    Smt: Software-defined memory tiering for heterogeneous computing systems with cxl memory expander,

    K. D. Kim, H. Kim, J. So, W. Lee, J.-H. Im, S.-R. Y .-C. Park, J. Cho, and H. U. Song, “Smt: Software-defined memory tiering for heterogeneous computing systems with cxl memory expander,” IEEE Micro, vol. 43, pp. 20–29, 2023. [Online]. Available: https://api.semanticscholar.or...

    2023

  30. [38]

    Ultrafast and memory-efficient alignment of short dna sequences to the human genome,

    B. Langmead, C. Trapnell, M. Pop, and S. L. Salzberg, “Ultrafast and memory-efficient alignment of short dna sequences to the human genome,” Genome Biology , vol. 10, pp. R25 – R25, 2009. [Online]. Available: https://api.semanticscholar.org/CorpusID:5057

    2009

  31. [39]

    T-cat: Dynamic cache allocation for tiered memory systems with memory interleaving,

    H. Lee, S. Lee, Y . Jung, and D. Kim, “T-cat: Dynamic cache allocation for tiered memory systems with memory interleaving,” IEEE Computer Architecture Letters , vol. 22, pp. 73–76, 2023. [Online]. Available: https://api.semanticscholar.org/CorpusID:259729055

    2023

  32. [40]

    Pond: Cxl-based memory pooling systems for cloud platforms,

    H. Li, D. S. Berger, S. Novakovic, L. R. Hsu, D. Ernst, P. Zardoshti, M. Shah, S. Rajadnya, S. Lee, I. Agarwal, M. D. Hill, M. Fontoura, and R. Bianchini, “Pond: Cxl-based memory pooling systems for cloud platforms,” Proceedings of the 28th ACM International Conference on Arch...

    2022

  33. [41]

    Heterospark: A heterogeneous cpu/gpu spark platform for machine learning algorithms,

    P. Li, Y . Luo, N. Zhang, and Y . Cao, “Heterospark: A heterogeneous cpu/gpu spark platform for machine learning algorithms,” 2015 IEEE In- ternational Conference on Networking, Architecture and Storage (NAS) , pp. 347–348, 2015

    2015

  34. [42]

    Dramsim3: A cycle-accurate, thermal-capable dram simulator,

    S.-J. Li, Z. Yang, D. Reddy, A. Srivastava, and B. Jacob, “Dramsim3: A cycle-accurate, thermal-capable dram simulator,” IEEE Computer Architecture Letters, vol. 19, pp. 106–109, 2020. [Online]. Available: https://api.semanticscholar.org/CorpusID:214356880

    2020

  35. [43]

    Ltd., “Redis,” https://redis .io, 2024

    R. Ltd., “Redis,” https://redis .io, 2024

    2024

  36. [44]

    Tpp: Transparent page placement for cxl- enabled tiered-memory,

    H. A. Maruf, H. Wang, A. Dhanotia, J. Weiner, N. Agarwal, P. Bhattacharya, C. Petersen, M. Chowdhury, S. O. Kanaujia, and P. Chauhan, “Tpp: Transparent page placement for cxl- enabled tiered-memory,” Proceedings of the 28th ACM International Conference on Architectural Support...

    2022

  37. [45]

    Climatelearn: Benchmarking machine learning for weather and climate modeling,

    T. Nguyen, J. Jewik, H. Bansal, P. Sharma, and A. Grover, “Climatelearn: Benchmarking machine learning for weather and climate modeling,” ArXiv, vol. abs/2307.01909, 2023. [Online]. Available: https://api.semanticscholar.org/CorpusID:259342316

    2023 arXiv

  38. [46]

    Gpt-4 technical report,

    OpenAI, “Gpt-4 technical report,” ArXiv, vol. abs/2303.08774, 2023

    2023 arXiv

  39. [47]

    Zero-infinity: Breaking the gpu memory wall for extreme scale deep learning,

    S. Rajbhandari, O. Ruwase, J. Rasley, S. Smith, and Y . He, “Zero-infinity: Breaking the gpu memory wall for extreme scale deep learning,” SC21: International Conference for High Performance Computing, Networking, Storage and Analysis, pp. 1–15, 2021. [Online]. Available: http...

    2021

  40. [48]

    Compressing dma engine: Leveraging activation sparsity for training deep neural networks,

    M. Rhu, M. O’Connor, N. Chatterjee, J. Pool, and S. W. Keckler, “Compressing dma engine: Leveraging activation sparsity for training deep neural networks,” 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA) , pp. 78–91, 2017. [Online]. Available...

    2018

  41. [49]

    Compute express link®: An open industry-standard interconnect enabling heterogeneous data-centric computing,

    D. D. Sharma, “Compute express link®: An open industry-standard interconnect enabling heterogeneous data-centric computing,” 2022 IEEE Symposium on High-Performance Interconnects (HOTI) , pp. 5– 12, 2022. [Online]. Available: https://api.semanticscholar.org/CorpusID: 252997701

    2022

  42. [50]

    Introducing compute express link™ (cxl™) 3.1: Significant improvements in fabric connectivity, mem- ory ras, security and more!

    D. D. Sharma and M. Wagh, “Introducing compute express link™ (cxl™) 3.1: Significant improvements in fabric connectivity, mem- ory ras, security and more!” https://computeexpresslink .org/wp-content/ uploads/2023/12/CXL 3.1-White-Paper FINAL.pdf, 2023

    2023

  43. [51]

    Review, analysis, and implementation of path selection strategies for 2d nocs,

    R. Singh, M. K. Bohra, P. Hemrajani, A. Kalla, D. P. Bhatt, N. Purohit, and M. Daneshtalab, “Review, analysis, and implementation of path selection strategies for 2d nocs,” IEEE Access , vol. 10, pp. 129 245– 129 268, 2022. [Online]. Available: https://api .semanticscholar.org...

    2022

  44. [52]

    Shortest-path queries in static networks,

    C. Sommer, “Shortest-path queries in static networks,” ACM Computing Surveys (CSUR) , vol. 46, pp. 1 – 31, 2014. [Online]. Available: https://api.semanticscholar.org/CorpusID:1384190

    2014

  45. [53]

    Bzsim: Fast, large-scale microarchitectural simulation with detailed interconnect modeling,

    P. Strikos, A. Ejaz, and I. Sourdis, “Bzsim: Fast, large-scale microarchitectural simulation with detailed interconnect modeling,” 2024 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) , pp. 167–178, 2024. [Online]. Available: https://api.s...

    2024

  46. [54]

    A processor-dma-based memory copy hardware accelerator,

    W. Su, L. Wang, M. Su, and S. Liu, “A processor-dma-based memory copy hardware accelerator,” 2011 IEEE Sixth International Conference on Networking, Architecture, and Storage, pp. 225–229, 2011. [Online]. Available: https://api.semanticscholar.org/CorpusID:26197371

    2011

  47. [55]

    Demystifying cxl memory with genuine cxl-ready systems and devices,

    Y . Sun, Y . Yuan, Z. Yu, R. Kuper, C. Song, J. Huang, H. Ji, S. Agarwal, J. Lou, I. Jeong, R. Wang, J. H. Ahn, T. Xu, and N. S. Kim, “Demystifying cxl memory with genuine cxl-ready systems and devices,” 2023 56th IEEE/ACM International Symposium on Microarchitecture (MICRO), ...

    2023

  48. [56]

    Mqsim: A framework for enabling realistic studies of modern multi-queue ssd devices,

    A. Tavakkol, J. G ´omez-Luna, M. Sadrosadati, S. Ghose, and O. Mutlu, “Mqsim: A framework for enabling realistic studies of modern multi-queue ssd devices,” in USENIX Conference on File and Storage Technologies , 2018. [Online]. Available: https: //api.semanticscholar.org/Corp...

    2018

  49. [57]

    XSBench - the development and verification of a performance abstraction for Monte Carlo reactor analysis,

    J. R. Tramm, A. R. Siegel, T. Islam, and M. Schulz, “XSBench - the development and verification of a performance abstraction for Monte Carlo reactor analysis,” in PHYSOR 2014 - The Role of Reactor Physics toward a Sustainable Future , Kyoto, 2014. [Online]. Available: https://...

    2014

  50. [58]

    A hybrid selection strategy based on traffic analysis for improving performance in networks on chip,

    M. Trik, A. M. N. G. Molk, F. Ghasemi, and P. Pouryeganeh, “A hybrid selection strategy based on traffic analysis for improving performance in networks on chip,” J. Sensors, vol. 2022, pp. 1–19, 2022. [Online]. Available: https://api.semanticscholar.org/CorpusID:248448066

    2022

  51. [59]

    Speedy transactions in multicore in-memory databases,

    S. Tu, W. Zheng, E. Kohler, B. H. Liskov, and S. Madden, “Speedy transactions in multicore in-memory databases,” Proceedings of the Twenty-Fourth ACM Symposium on Operating Systems Principles, 2013. [Online]. Available: https://api.semanticscholar.org/CorpusID:10076139

    2013

  52. [60]

    An empirical guide to the behavior and use of scalable persistent memory,

    J. Yang, J. Kim, M. Hoseinzadeh, J. Izraelevitz, and S. Swanson, “An empirical guide to the behavior and use of scalable persistent memory,” login Usenix Mag. , vol. 45, 2019. [Online]. Available: https://api.semanticscholar.org/CorpusID:199543286

    2019

  53. [61]

    Overcoming the memory wall with cxl- enabled ssds,

    S.-P. Yang, M. Kim, S. Nam, J. Park, J. yong Choi, E. H. Nam, E. Lee, S. Lee, and B. S. J. Kim, “Overcoming the memory wall with cxl- enabled ssds,” in USENIX Annual Technical Conference, 2023. [Online]. Available: https://api.semanticscholar.org/CorpusID:259859173

    2023

  54. [62]

    Cxlmemsim: A pure software simulated cxl.mem for performance characterization,

    Y . Yang, P. Safayenikoo, J. Ma, T. A. Khan, and A. Quinn, “Cxlmemsim: A pure software simulated cxl.mem for performance characterization,” ArXiv, vol. abs/2303.06153, 2023. [Online]. Available: https://api.semanticscholar.org/CorpusID:257496563

    2023 arXiv

  55. [63]

    Stable machine-learning parameterization of subgrid processes for climate modeling at a range of resolutions,

    J. Yuval and P. A. O’Gorman, “Stable machine-learning parameterization of subgrid processes for climate modeling at a range of resolutions,” Nature Communications , vol. 11, 2020. [Online]. Available: https: //api.semanticscholar.org/CorpusID:220311961

    2020

  56. [64]

    G10: Enabling an efficient unified gpu memory and storage architecture with smart tensor migrations,

    H. Zhang, Y . E. Zhou, Y . Xue, Y . Liu, and J. Huang, “G10: Enabling an efficient unified gpu memory and storage architecture with smart tensor migrations,” 2023 56th IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 395–410, 2023. [Online]. Available: https:...

    2023

  57. [65]

    Zng: Architecting gpu multi-processors with new flash for scalable data analysis,

    J. Zhang and M. Jung, “Zng: Architecting gpu multi-processors with new flash for scalable data analysis,” 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA) , pp. 1064–1075, 2020. [Online]. Available: https://api .semanticscholar.org/ CorpusID:219103734

    2020

  58. [66]

    Mpress: Democratizing billion-scale model training on multi- gpu servers via memory-saving inter-operator parallelism,

    Q. Zhou, H. Wang, X. Yu, C. Li, Y . Bai, F. Yan, and Y . Xu, “Mpress: Democratizing billion-scale model training on multi- gpu servers via memory-saving inter-operator parallelism,” 2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA) , pp. 556–56...

    2023

  59. [2008]

    Available: https://api .semanticscholar.org/CorpusID: 14530113

    [Online]. Available: https://api .semanticscholar.org/CorpusID: 14530113

  60. [2011]

    Available: https://doi .org/10.1145/2024716.2024718

    [Online]. Available: https://doi .org/10.1145/2024716.2024718

Pith tools

Reviewed August 12, 2026 · model on record in the stance chip above.