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arxiv: 1907.00766 · v1 · pith:SRAPGSMQnew · submitted 2019-07-01 · 📡 eess.SP

Design and Implementation of a Neural Network Based Predistorter for Enhanced Mobile Broadband

Chance Tarver , Alexios Balatsoukas-Stimming , Joseph R. Cavallaro This is my paper

Pith reviewed 2026-05-25 11:41 UTC · model grok-4.3

classification 📡 eess.SP
keywords digital predistortionneural networkFPGAmemory polynomialadjacent channel leakage ratioerror vector magnitudewireless transmitterpredistorter
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The pith

Neural network predistorter with direct training cuts FPGA latency 42% and boosts throughput 9.6% over memory polynomials.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper shows that a neural network can correct nonlinearities in wireless RF transmitters more effectively than traditional polynomial models when trained with a method that skips the indirect learning architecture. This yields measurable gains in adjacent channel leakage ratio and error vector magnitude. On an FPGA accelerator the neural network version runs with 42% lower latency, 9.6% higher throughput, and 15% fewer multiplications per sample than a memory-polynomial design of comparable performance.

Core claim

A neural network based predistorter trained without the indirect learning architecture improves both adjacent channel leakage ratio and error vector magnitude while delivering a 42% reduction in latency, 9.6% increase in throughput, and 15% fewer multiplications per sample on an FPGA accelerator compared with a similarly performing memory-polynomial implementation.

What carries the argument

The novel neural network training method that avoids the indirect learning architecture, allowing direct optimization of the predistorter for the transmitter's nonlinear response.

If this is right

  • Transmitters can maintain higher output power while meeting emission masks because of lower adjacent channel leakage.
  • FPGA-based baseband processing becomes faster and uses fewer resources for the same predistortion quality.
  • Mobile broadband devices can achieve better power efficiency by operating the power amplifier closer to its saturation region.
  • Real-time predistortion becomes feasible with lower computational cost per transmitted sample.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same direct-training approach may extend to other real-time nonlinear compensation tasks such as amplifier linearization in satellite or radar systems.
  • Hardware savings could allow predistortion to be added to lower-cost or lower-power chipsets that previously could not afford polynomial implementations.
  • If the training remains stable across temperature and aging, the technique could reduce the frequency of recalibration cycles in deployed base stations.

Load-bearing premise

The new training procedure for the neural network produces the reported improvements in leakage ratio, error vector magnitude, and hardware metrics without depending on indirect learning.

What would settle it

Side-by-side ACLR and EVM measurements on the same test signals and FPGA hardware for the neural network predistorter using the direct training method versus the same network trained with the indirect learning architecture.

Figures

Figures reproduced from arXiv: 1907.00766 by Alexios Balatsoukas-Stimming, Chance Tarver, Joseph R. Cavallaro.

Figure 2
Figure 2. Figure 2: General structure of the DPD and PA neural networks [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Example of iterative NN-DPD training for two train [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figure 5
Figure 5. Figure 5: EVM vs. number of real multiplications for NN DPD (s [PITH_FULL_IMAGE:figures/full_fig_p004_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Example spectrum for the M = 4 polynomial and K = 1 NN. Each of these use around 80 multiplications per time-domain input sample to the DPD. Reducing EVM can improve reception quality and is hence a desirable result. The EVM is computed as EVM = kˆs − sk ksk × 100%, (11) where s is the vector of all original symbols mapped onto complex constellations on OFDM subcarriers in the frequency domain, ˆs is the c… view at source ↗
Figure 7
Figure 7. Figure 7: Here, each wire corresponds to a 16-bit bus. The real [PITH_FULL_IMAGE:figures/full_fig_p005_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Example structure of a PE for the ith neuron in hidden layer 1. B. Polynomial Accelerator The memory polynomial is also implemented using 16 bits throughout the design. We target the design for maximum throughput by fully parallelizing and pipelining it so that a new time-domain input sample can streamed in each clock cycle. The main overall structure of the design is shown in [PITH_FULL_IMAGE:figures/ful… view at source ↗
Figure 9
Figure 9. Figure 9: Each polynomial “branch” of the memory polynomial [PITH_FULL_IMAGE:figures/full_fig_p005_9.png] view at source ↗
Figure 9
Figure 9. Figure 9: General structure of the high-throughput, low-la [PITH_FULL_IMAGE:figures/full_fig_p006_9.png] view at source ↗
read the original abstract

Digital predistortion is the process of correcting for nonlinearities in the analog RF front-end of a wireless transmitter. These nonlinearities contribute to adjacent channel leakage, degrade the error vector magnitude of transmitted signals, and often force the transmitter to reduce its transmission power into a more linear but less power-efficient region of the device. Most predistortion techniques are based on polynomial models with an indirect learning architecture which have been shown to be overly sensitive to noise. In this work, we use neural network based predistortion with a novel neural network training method that avoids the indirect learning architecture and that shows significant improvements in both the adjacent channel leakage ratio and error vector magnitude. Moreover, we show that, by using a neural network based predistorter, we are able to achieve a 42% reduction in latency and 9.6% increase in throughput on an FPGA accelerator with 15% fewer multiplications per sample when compared to a similarly performing memory-polynomial implementation.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

1 major / 0 minor

Summary. The paper proposes a neural network-based digital predistorter for correcting nonlinearities in RF transmitters for enhanced mobile broadband. It introduces a novel training method that avoids the indirect learning architecture, claiming significant improvements in adjacent channel leakage ratio (ACLR) and error vector magnitude (EVM). The work further reports an FPGA implementation achieving 42% latency reduction, 9.6% throughput increase, and 15% fewer multiplications per sample compared to a similarly performing memory-polynomial baseline.

Significance. If the reported performance gains and hardware metrics hold under detailed scrutiny, the approach could offer a practical alternative to polynomial-based predistortion with advantages in efficiency and signal quality for 5G transmitters. The FPGA results, if reproducible, would be a strength for implementation-focused work in signal processing.

major comments (1)
  1. [Abstract] Abstract: The central quantitative claims (42% latency reduction, 9.6% throughput increase, 15% fewer multiplications, and ACLR/EVM improvements from the novel training method) are stated without any supporting data, figures, tables, or methodological details in the provided manuscript text, rendering the claims unverifiable and load-bearing for the paper's contribution.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for the detailed review and constructive comments on our manuscript. We address the major comment point by point below.

read point-by-point responses

  1. Referee: [Abstract] Abstract: The central quantitative claims (42% latency reduction, 9.6% throughput increase, 15% fewer multiplications, and ACLR/EVM improvements from the novel training method) are stated without any supporting data, figures, tables, or methodological details in the provided manuscript text, rendering the claims unverifiable and load-bearing for the paper's contribution.

    Authors: The abstract serves as a high-level summary of the key contributions and results. The supporting data, figures, tables, and methodological details for the reported ACLR/EVM improvements from the novel training method, as well as the FPGA metrics (42% latency reduction, 9.6% throughput increase, and 15% fewer multiplications per sample versus the memory-polynomial baseline), are provided in the full manuscript body. These appear in the sections on the proposed neural network predistorter, the novel training approach, experimental setup, performance evaluation, and hardware implementation results, including direct comparisons and resource utilization data. If the version provided to the referee omitted these sections or figures, we will ensure the complete manuscript is resubmitted. We can also revise the abstract to include explicit cross-references to the relevant sections and figures for improved verifiability. revision: partial

Circularity Check

0 steps flagged

No significant circularity; empirical implementation study

full rationale

The paper reports FPGA hardware metrics (latency, throughput, multiplications) and ACLR/EVM improvements from a neural-network predistorter versus a memory-polynomial baseline, plus a training method that avoids indirect learning. These are direct empirical measurements and comparisons against external baselines, not derived quantities obtained by fitting parameters to the target result or by self-citation chains. No equations, uniqueness theorems, or ansatzes are invoked that reduce to the paper's own inputs. The work is self-contained against external benchmarks.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

No details available from abstract regarding free parameters, axioms, or invented entities.

pith-pipeline@v0.9.0 · 5707 in / 854 out tokens · 29790 ms · 2026-05-25T11:41:51.777801+00:00 · methodology

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Reference graph

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