REVIEW
Development of a PCI Based Data Acquisition Platform for High Intensity Accelerator Experiments
Not yet reviewed by Pith; the record is open.
This paper has not been read by Pith yet. Machine review is queued; the pith claim, tier, and objections will appear here once it completes.
SPECIMEN: schema-true, not a live event
T0 review · schema-true
One-sentence machine reading of the paper's core claim.
pith:XXXXXXXX · record.json · timestamp
read the original abstract
Data logging at an upgraded KEKB accelerator or the J-PARC facility, currently under commission, requires a high density data acquisition platform with integrated data reduction CPUs. To follow market trends, we have developed a DAQ platform based on the PCI bus, a choice which permits a fast DAQ and a long expected lifetime of the system. The platform is a 9U-VME motherboard consisting of four slots for signal digitization modules, readout FIFOs for data buffering, and three PMC slots, on one of which resides a data reduction CPU. We have performed long term and thermal stability tests. The readout speed on the platform has been measured up to 125 MB/s in DMA mode.
Discussion (0). Sign in to comment.