Automated Design Space Exploration of CGRA Processing Element Architectures using Frequent Subgraph Analysis
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The architecture of a coarse-grained reconfigurable array (CGRA) processing element (PE) has a significant effect on the performance and energy efficiency of an application running on the CGRA. This paper presents an automated approach for generating specialized PE architectures for an application or an application domain. Frequent subgraphs mined from a set of applications are merged to form a PE architecture specialized to that application domain. For the image processing and machine learning domains, we generate specialized PEs that are up to 10.5x more energy efficient and consume 9.1x less area than a baseline PE.
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DICE: Enabling Efficient General-Purpose SIMT Execution with Statically Scheduled Coarse-Grained Reconfigurable Arrays
DICE achieves 1.77-1.90x dynamic energy efficiency and 42-46% power reduction versus modeled NVIDIA Turing SMs by executing SIMT workloads on pipelined CGRAs with p-graphs handling dynamism and 68% fewer register file...
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