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REVIEW 3 major objections 6 minor 60 references

Wavelet Based Frequency Detection Using FPGAs

T0 review · 3 major / 6 minor · reviewed 2026-08-10 · deepseek-v4-flash

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Pith's one-line read This paper claims that a pre-generated complex Morlet wavelet, convolved in real time with 14-bit samples from an FPGA's ADC, can detect the presence of a 6 kHz tone reliably enough to be read off eight LEDs.

desk verdict An honest student demo of a standard Morlet-FIR tone detector; the feasibility story is plausible but the only evidence is an unexplained visual LED curve. read the letter →

arxiv 2412.20351 v1 pith:UGOMRB6T submitted 2024-12-29 cs.AR

Caleb Hill , Darshika G. Perera This is my paper · ORCID
classification cs.AR
keywords wavelettransformMorletfrequencydetectionFPGAreal-timeconvolutionanalog-to-digitalconverterLEDthresholdfiniteimpulseresponsefilter
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper claims that a continuous wavelet transform can be implemented on a low-cost FPGA as a real-time frequency detector, and that the approach is practical: a 6 kHz tone in the ADC input produces a clear, visually observable response. The authors build a 133-tap finite impulse response filter whose coefficients are a pre-generated complex Morlet wavelet, convolve it sample-by-sample with 14-bit ADC data, and display the magnitude-squared output on eight LEDs. They argue this replaces the active local oscillator of a software-defined radio with a set of stored coefficients, so no signal generation is needed on the hardware. The claim matters because frequency detection is usually compute-intensive, and an FPGA implementation could move such detection into compact, low-power embedded systems.

What carries the argument

The central mechanism is a complex Morlet wavelet, a Gaussian-tapered sine oscillation with real and imaginary parts, pre-generated in software and scaled to 14-bit integers. The FPGA stores 133 of these coefficients for each part and treats them as a finite impulse response filter: each new ADC sample shifts into a 133-deep delay line, the samples are multiplied by the coefficients, and the real and imaginary products are accumulated separately. Squaring and summing the two accumulators yields the magnitude-squared response, which is compared to eight evenly spaced thresholds that light one LED per level. This gives a sample-by-sample time-frequency output without a phase-locked oscillator.

What would settle it

Run a constant-amplitude sine sweep from 4 to 8 kHz through the ADC and record which LEDs light: if LEDs activate at frequencies well outside the 6 kHz band, or stay dark across 6 kHz, the claim that the wavelet filter detects the target frequency is false.

Watch

Extended reading notes

Core claim

On the paper's own terms, the central discovery is that pre-generated wavelet coefficients, stored as 14-bit integers and convolved with a real-time 14-bit sample stream, act as a frequency-selective receiver: the magnitude-squared response rises when the input contains a 6 kHz component and falls otherwise, and this change can be rendered on LEDs. The experiment demonstrates the full chain from analog input through the FPGA's on-board ADC, through the wavelet filter, to a visible output, showing that no active oscillator or quadrature receiver is required for spectral detection at a chosen frequency.

Load-bearing premise

The load-bearing premise is that the 14-bit simulation used to set the eight LED thresholds predicts the actual hardware response; if real ADC noise or the bit-clipping workaround shifts those thresholds, the LED pattern may not show true frequency selectivity.

Editorial extensions

If this is right

  • A single-frequency wavelet detector can be built on a small FPGA with only stored coefficients, a delay line, multipliers, and accumulators; no local oscillator or quadrature mixer is required.
  • Retuning the detector to another frequency only requires regenerating the coefficient file and loading it into the header; the Verilog logic stays the same.
  • Detecting lower frequencies needs longer wavelets, so on the Spartan-3E a 1 kHz detector would require roughly 1,600 coefficients and exceed the board's resources; this sets the practical frequency range and bit-depth trade-offs.
  • A binary frequency-shift-keying demodulator is a plausible next implementation on the same hardware if the ADC bit depth is reduced or wavelets are shortened.
  • The flow of testing in high-resolution simulation, then 14-bit simulation, then hardware, let the authors set LED thresholds before touching the board, which is why they call the process rapid prototyping.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • A natural next test is to measure the detector's passband width and false-alarm rate on noise, since the paper reports a single frequency sweep without quantifying selectivity.
  • The same stored-coefficient architecture should generalize to a bank of wavelets, turning the FPGA into a coarse spectrum analyzer whose band spacing is set by coefficient generation rather than analog hardware.
  • The 50-bit comparison failure implies the clipping fix reshapes the response curve; porting to a newer FPGA with wider native datapaths might restore full dynamic range without clipping.
  • Because the thresholds were derived from simulation, a hardware calibration pass would reveal any systematic offset from ADC noise or pre-amplifier gain, and would make the LED display a trustworthy power indicator.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 6 minor

Summary. The manuscript reports an FPGA implementation of wavelet-based frequency detection targeting a 6 kHz tone. The design uses a Spartan-3E board's ADC to sample a signal at 20 kSps, feeds the 14-bit samples into a 133-tap complex Morlet wavelet filter (real and imaginary coefficient streams), computes the magnitude-squared response, and drives eight LEDs through thresholds derived from 14-bit Python simulations. The authors report a working system and present an LED-activation-versus-frequency curve as evidence that wavelet-based spectral detection is possible and easily implemented on an FPGA.

Significance. If validated quantitatively, the paper would provide a useful case study in lightweight FPGA-based spectral detection: it demonstrates a full signal chain from ADC sampling through a complex FIR convolution to a visual response, and it documents practical hardware issues (SPI timing, large-bit comparisons) that are often absent from idealized descriptions. The working board and the reported response curve are genuine strengths, as is the attempt to pre-verify the design in Python before hardware implementation. However, the current evidence is a single qualitative LED display, with no quantitative error analysis, no repeated trials, no false-alarm assessment, and no comparison against an independent baseline. Consequently, the abstract's claim that the experiment 'demonstrates' wavelet-based detection is stronger than the data currently support, and the broader contribution to the field remains preliminary.

major comments (3)
  1. [§4, Figure 9] The only experimental evidence for the central claim is a qualitative LED-activation curve. The paper provides no numeric measurements of the wavelet magnitude response versus frequency, no repeated trials, no false-alarm or miss-rate analysis, and no comparison with the simulated response shown in Figure 5. Without such quantitative support, the claim in the abstract that the experiment 'demonstrates that wavelet-based spectral detection is both possible, and easily implemented' is not fully supported by the data presented.
  2. [§3, LED Control Module / Wavelet Module] The paper reports that 50-bit signed comparisons 'always yielded a TRUE output' for any positive response, and the adopted fix was to clip the 34 least-significant bits from the thresholds and compare only bits 49..32 of the response. Because the root cause is explicitly left as future work ('all three will warrant future research'), there is no demonstrated guarantee that the truncated comparison is monotonic in the true magnitude-squared response. The LED pattern in Figure 9 could therefore reflect an artifact of the comparison path rather than the wavelet filter's frequency selectivity. Please provide ChipScope traces of the raw response and threshold values, or otherwise validate that the clipping preserves the intended ordering.
  3. [§2, Conceptual Approach; §3, LED Control Module] The eight LED thresholds are taken entirely from 14-bit Python simulations (Figure 5), not from hardware measurements, and the hardware debugging included modifications to the SPI timing and read counter of the ADC module. If the simulation and hardware responses differ, the threshold crossings that produce Figure 9 do not constitute an independent confirmation of 6 kHz detection. The manuscript should either calibrate the thresholds against measured hardware responses or report the raw hardware response curve so that the selectivity claim can be verified directly.
minor comments (6)
  1. [§2, Figure 3 caption] The caption reads 'Wavelet Response to Chip Signal'; 'chip' should be 'chirp'.
  2. [§3, throughout] There are multiple typographical errors, including 'Therefor' for 'Therefore', 'deboucer' for 'debouncer', and 'form' for 'from'. A careful proofread is needed.
  3. [§2, Equation 3] The Morlet wavelet parameters (the Gaussian width sigma and the number of oscillations under the taper) are not specified numerically, although the text states that the Gaussian width is crucial. Please state the exact values used to generate the coefficients in Figure 2.
  4. [§4, Figure 9] Figure 9 lacks axis labels and a legend; please label the horizontal axis with input frequency (in kHz) and the vertical axis with the number of LEDs or a normalized response scale.
  5. [References] Several references are incomplete (e.g., [1] and [10] lack a venue or publisher, and [6] and [8] lack author names). Please complete the bibliographic entries.
  6. [§3, Pre-Amp and ADC Module] The repeated references to 'homework assignment 7' are not appropriate for an archival paper; replace them with a description of the prior design or a citation.

Circularity Check

1 steps flagged · score 2.0 of 10

Minor circularity: LED detection thresholds are calibrated to the same simulation being demonstrated, but the central feasibility claim rests on the independently defined wavelet convolution.

  1. fitted input called prediction [Section 3, LED Control Module / Wavelet Module; Figure 9 in Section 4]
    "The threshold values were determined in the experimental stage with 14-bit simulation data measuring the maximum response of a full-range signal at the target frequency. The maximum value was divided by 8 to segment the dynamic range into 8 divisions for the 8 LEDs onboard the Spartan 3e, and the threshold values were shifted down by a further one-sixteenth the max response value so place the final thresholds in the middle of each range."

    The eight LED thresholds are derived from the peak magnitude-squared response of the same 14-bit Python simulation of the wavelet that the hardware demonstration is meant to validate. Therefore the Figure 9 LED-activation-versus-frequency curve is a binarized rendering of the simulation's expected response: if the FPGA arithmetic tracks the simulation, LEDs will turn on near 6 kHz by construction, rather than as an independent prediction. This is a display calibration, not a fitted parameter feeding a quantitative claim; the wavelet coefficients are defined independently from the standard Morlet wavelet, so the core feasibility result does not reduce to the threshold fit. The circularity is limited to the strength of Figure 9 as evidence of frequency selectivity.

full rationale

The paper's central claim is a feasibility demonstration: a pre-generated complex Morlet wavelet convolved with a real-time ADC stream on a Spartan-3E can indicate the presence of a 6 kHz tone. The convolution itself is defined from the standard Morlet wavelet (eq. 3) and independently checked in Python against stationary and chirp signals. The only fitted quantities are the eight LED thresholds, taken from 14-bit simulation of the same wavelet; these thresholds do not feed back into the wavelet coefficients or the magnitude-squared computation, so they serve only as display levels. Thus the LED curve is a calibrated visualization, not a numerical prediction, and the central claim does not reduce to the fit. There is a mild circular flavor in that Figure 9 cannot independently confirm the wavelet's frequency selectivity, only that the hardware response tracks the simulation. The unexplained 50-bit comparison failure and the bit-clipping fix are correctness risks rather than circularity: they weaken the link between the LED pattern and the true wavelet response but do not make any argument self-referential. Extensive self-citations to the UCCS group support background assertions about FPGA suitability and are not load-bearing for the wavelet-convolution result. Overall circularity is low.

Assumptions & free parameters 4 free parameters · 5 assumptions · 0 invented entities

The design uses a hand-chosen target frequency, a hand-chosen tap count and sampling rate, and simulation-derived thresholds. The exact wavelet shape parameters are not stated. No new entities are postulated.

free parameters (4)
  • Number of FIR taps = 133
    Chosen to balance frequency selectivity against Spartan 3E resource limits; the paper notes that a 1 kHz target would require 1596 coefficients, exceeding resources.
  • ADC sampling rate = 20 kSps
    Chosen to keep the tap count low; 20 kSps is above the Nyquist rate for 6 kHz but the rate also affects the wavelet scale in samples.
  • LED threshold scaling = max_response/8, shifted down by max_response/16
    Thresholds were derived from 14-bit simulations of the same wavelet and full-range signal, then used to define detection in hardware.
  • Wavelet scale parameters (sigma and oscillation count) = not stated in paper
    The Gaussian width and carrier parameters of the Morlet wavelet are not given numerically; figure 2 and equation 3 are the only descriptions, and these values determine the frequency response.
assumptions (5)
  • domain assumption Convolution of a real signal with a complex Morlet wavelet produces a response whose magnitude indicates the presence of the wavelet's center frequency.
    This is the core signal-processing premise; the paper relies on it to interpret the LED response as frequency detection.
  • domain assumption The 14-bit ADC and signed arithmetic model the signal faithfully enough that simulation-derived thresholds transfer to hardware.
    Thresholds were determined in simulation and used without hardware calibration; the paper assumes the hardware response matches simulation.
  • domain assumption The Spartan 3E FPGA resources are sufficient for a 133-tap complex FIR filter.
    The design succeeds only because the tap count fits; the paper notes that larger tap counts exceed resources.
  • domain assumption The input sweep signal covers the wavelet's responsive range with sufficient amplitude to cross thresholds.
    Figure 9 shows LED activation vs. frequency; this assumes the test signal is representative and the LED display is a valid measurement.
  • standard math Nyquist sampling theorem applies to the 20 kSps ADC sampling.
    The paper uses this to justify that a 6 kHz signal is not aliased; it is standard.

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Pith. "Pith review of Wavelet Based Frequency Detection Using FPGAs." pith.science (2026). https://pith.science/paper/UGOMRB6T

@misc{pith2026241220351,
  author       = {Pith},
  title        = {Pith review of: Wavelet Based Frequency Detection Using FPGAs},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/UGOMRB6T}},
  note         = {Machine review of arXiv:2412.20351}
}
read the original abstract

In the realm of signal processing, frequency and spectrum detection are fundamental tasks that can be computationally intensive. This project leverages the power of FPGAs to perform wavelet analysis on an input signal. The goal is to detect the presence of a specific frequency component - in this case, 6 kHz. Our experiments demonstrate that wavelet-based spectral detection is both possible, and easily implemented using an FPGA.

Discussion (0). Continue with ORCID to comment.

Reference graph

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Pith tools

Reviewed August 10, 2026 · model on record in the stance chip above.