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A Low-Power 1 Gb/s Line Driver with Configurable Pre-Emphasis for Lossy Transmission Lines

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arxiv 2210.11882 v1 pith:V7W7BC4X submitted 2022-10-21 cs.AR eess.SP

Nicholas St. John , Soumyajit Mandal , Grzegorz W. Deptuch , Eric Raguzin , Sergio Rescia This is my paper · ORCID
classification cs.AReess.SP
keywords driverconfigurablelinepre-emphasisamplitudearchitecturearraycmos
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A line driver with configurable pre-emphasis is implemented in a 65 nm CMOS process. The driver utilizes a three-tap feed-forward equalization (FFE) architecture. The relative delays between the taps are selectable in increments of 1/16th of the unit interval (UI) via an 8-stage delay-locked loop (DLL) and digital interpolator. It is also possible to control the output amplitude and source impedance for each tap via a programmable array of eight source-series terminated (SST) drivers. The entire design consumes 9 mW from a 1.2 V supply at 1 Gb/s.

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