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ARM SVE Unleashed: Performance and Insights Across HPC Applications on Nvidia Grace

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arxiv 2505.09462 v1 pith:VTUJETTC submitted 2025-05-14 cs.DC

classification cs.DC
keywords performancevectorapplicationsexploitinggraceproposeprovidesacross
verification ladder T0 review T1 audit T2 compute T3 formal
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Vector architectures are essential for boosting computing throughput. ARM provides SVE as the next-generation length-agnostic vector extension beyond traditional fixed-length SIMD. This work provides a first study of the maturity and readiness of exploiting ARM and SVE in HPC. Using selected performance hardware events on the ARM Grace processor and analytical models, we derive new metrics to quantify the effectiveness of exploiting SVE vectorization to reduce executed instructions and improve performance speedup. We further propose an adapted roofline model that combines vector length and data elements to identify potential performance bottlenecks. Finally, we propose a decision tree for classifying the SVE-boosted performance in applications.

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