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arxiv: 2607.00904 · v1 · pith:W77CN67Nnew · submitted 2026-07-01 · ⚛️ physics.ins-det

TD-Link: A Daisy-Chain Optical Architecture for Integrated Data Readout and Deterministic Timing Distribution in Large-Scale Detector Systems

Andrea Abba , Gianluca Becuzzi , Matteo Bianchini , Francesco Caponio , Stefano Carsi , Alberto Cusimano , Camilla Maggio , Annalisa Mati
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Daniele Ninci Andrea Picchi Carlo Tintori
This is my paper

Pith reviewed 2026-07-02 03:08 UTC · model grok-4.3

classification ⚛️ physics.ins-det
keywords optical communicationtiming synchronizationdetector readoutdaisy-chain topologyphase alignmentdata concentratorsub-nanosecond timingPicoTDC
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The pith

A daisy-chain optical link synchronizes detector boards to 7-28 ps while carrying data and timing on one fiber.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

TD-Link combines high-speed data readout and precise timing distribution for large detector systems by sending both over a single optical fiber in a multidrop daisy-chain ring. Up to sixteen front-end boards connect per link through a token-based protocol at 3.125 Gb/s, with eight such links possible per concentrator. Transmitter phase is locked by treating the elastic buffer half-full state as a phase detector, DDMTD circuits correct inter-concentrator offsets, and zero-delay PLLs clean and forward the clock downstream. A reader would care because this approach cuts cabling while delivering the sub-nanosecond coherence required for accurate event reconstruction. Tests with PicoTDC boards show the synchronization holds across power cycles.

Core claim

TD-Link achieves board-to-board synchronization with a sigma of 7 ps when boards share a coaxial reference clock and below 28 ps when on independent concentrators through elastic-buffer phase locking, DDMTD offset compensation, and zero-delay PLL retransmission that preserves coherence along the chain.

What carries the argument

The half-full condition of the multi-gigabit transceiver elastic buffer used as a one-bit phase detector to iteratively adjust the transmit phase interpolator until FIFO write-to-read difference reaches half-depth.

If this is right

  • The topology supports up to 128 boards per concentrator with all data, synchronization, and control traffic in one serial stream.
  • Per-hop latency stays low through token passing and on-the-fly payload fragmentation.
  • Synchronization remains stable across repeated power cycles once alignment completes.
  • Recovered clocks are cleaned and forwarded to keep phase relations intact down the entire chain.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The single-fiber approach could lower infrastructure costs and complexity in other distributed scientific instruments that need both high data rates and precise timing.
  • The buffer-based phase lock technique might be tested on different transceiver families to check portability beyond the hardware used here.
  • Longer chains or higher board counts would need direct measurement to confirm that jitter does not accumulate beyond the reported levels.

Load-bearing premise

The elastic buffer half-full state reliably signals the desired deterministic transmit phase and the zero-delay PLL preserves phase coherence without adding jitter that affects the timing measurements.

What would settle it

A measured board-to-board synchronization sigma exceeding 30 ps under the reported alignment procedure and stable power conditions would show the timing performance claim does not hold.

Figures

Figures reproduced from arXiv: 2607.00904 by Alberto Cusimano, Andrea Abba, Andrea Picchi, Annalisa Mati, Camilla Maggio, Carlo Tintori, Daniele Ninci, Francesco Caponio, Gianluca Becuzzi, Matteo Bianchini, Stefano Carsi.

Figure 1
Figure 1. Figure 1: Pictorial view of a TD-Link readout system. A DT5215 Data Con [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: TD-Link master clock distribution as implemented in the DT5215 Data [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Multi-concentrator topology. A master concentrator distributes its [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figure 5
Figure 5. Figure 5: The GTP transceiver outputs 20-bit raw data words; [PITH_FULL_IMAGE:figures/full_fig_p003_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Principle of the DDMTD phase detector. The two clocks to be [PITH_FULL_IMAGE:figures/full_fig_p004_6.png] view at source ↗
Figure 5
Figure 5. Figure 5: FERS slave clock recovery. The transceiver CDR delivers a jittered [PITH_FULL_IMAGE:figures/full_fig_p004_5.png] view at source ↗
Figure 7
Figure 7. Figure 7: Dual-purpose conflict of the transmit Phase Interpolator in buffer [PITH_FULL_IMAGE:figures/full_fig_p005_7.png] view at source ↗
Figure 10
Figure 10. Figure 10: Baseline jitter measurement with the timing reference distributed via [PITH_FULL_IMAGE:figures/full_fig_p006_10.png] view at source ↗
Figure 9
Figure 9. Figure 9: Finite-state machine of the deterministic TX buffer alignment. Phase 1 [PITH_FULL_IMAGE:figures/full_fig_p006_9.png] view at source ↗
Figure 11
Figure 11. Figure 11: Time-difference distribution for two FERS boards on the same TD [PITH_FULL_IMAGE:figures/full_fig_p007_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: Time-difference distribution for two FERS boards on different TD [PITH_FULL_IMAGE:figures/full_fig_p007_12.png] view at source ↗
read the original abstract

TD-Link is a custom optical communication architecture that combines high-throughput data readout and sub-nanosecond timing synchronization over a single optical fiber for large-scale detector systems. The protocol adopts a multidrop daisy-chain ring topology connecting a Data Concentrator to up to sixteen FERS front-end boards per link, with up to eight independent links per concentrator. Operating at 3.125~Gb/s, TD-Link carries data, synchronization, and control traffic within the same serial stream through a token-based streaming protocol that minimizes per-hop latency and supports on-the-fly payload fragmentation. Transmitter lane alignment on the concentrator is achieved by exploiting the half-full condition of the multi-gigabit transceiver elastic buffer as a one-bit phase detector: a firmware finite-state machine iteratively adjusts the transmit phase interpolator until the FIFO write-to-read pointer difference reaches half-depth, locking each lane to a deterministic phase condition. A Digital Dual Mixer Time Difference (DDMTD) circuit is employed for inter-concentrator synchronization, measuring and compensating the phase offset between the recovered transceiver clock and the FPGA fabric reference clock. On the FERS boards, the recovered clock is cleaned by an external zero-delay PLL and retransmitted downstream, preserving phase coherence along the daisy chain. Experimental validation with CERN PicoTDC-equipped FERS boards demonstrates a board-to-board synchronization sigma of 7~ps for boards sharing a coaxial reference clock and below 28~ps for boards on independent concentrators. The results are stable across power cycles, confirming the robustness of the alignment strategy.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The manuscript presents TD-Link, a daisy-chain optical architecture operating at 3.125 Gb/s that integrates high-throughput data readout with deterministic sub-nanosecond timing distribution over a single fiber for large-scale detectors. It describes a token-based multidrop ring protocol connecting a Data Concentrator to up to 16 FERS boards per link, transmit-lane alignment via iterative firmware adjustment of the MGT phase interpolator until the elastic-buffer write/read pointer difference reaches half-depth, DDMTD-based inter-concentrator phase compensation, and zero-delay PLL clock cleaning/retransmission on each FERS board to maintain chain coherence. Experimental results obtained with CERN PicoTDC-equipped boards report board-to-board synchronization sigma of 7 ps when sharing a coaxial reference clock and below 28 ps across independent concentrators, with stability across power cycles.

Significance. If the reported synchronization performance is robustly supported, the work would offer a practical, low-cabling solution for combined readout and timing in next-generation HEP and nuclear-physics detectors, where picosecond-level determinism over optical links is increasingly required. The integration of phase alignment into standard MGT resources and the use of an external zero-delay PLL are pragmatic engineering choices that could be adopted by other groups.

major comments (2)
  1. [Abstract, §4] Abstract and §4 (experimental validation): the headline synchronization sigmas (7 ps shared-clock, <28 ps independent concentrators) rest on two unverified steps—the firmware FSM treating the elastic-buffer half-full flag as a reliable one-bit phase detector and the zero-delay PLL preserving deterministic phase without adding measurable jitter—yet no auxiliary data (phase histograms at lock, metastability checks, or direct PLL additive-jitter measurements) are supplied to confirm these assumptions hold at the claimed precision.
  2. [Abstract, §4] Abstract and §4: the experimental results lack any statement of the number of independent trials, measurement duration, statistical error analysis, or assessment of systematic effects (temperature drift, fiber-length variation, power-supply noise), which are required to substantiate the reported sigma values and the claim of stability across power cycles.
minor comments (2)
  1. The manuscript would benefit from a block diagram or timing diagram explicitly showing the elastic-buffer pointer difference and the DDMTD measurement points.
  2. Notation for the half-full threshold and the exact MGT phase-interpolator step size should be defined once in the text rather than only in the figure captions.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the thorough review and valuable feedback on our manuscript. We address the major comments point by point below and will incorporate revisions to strengthen the experimental validation section.

read point-by-point responses

  1. Referee: [Abstract, §4] Abstract and §4 (experimental validation): the headline synchronization sigmas (7 ps shared-clock, <28 ps independent concentrators) rest on two unverified steps—the firmware FSM treating the elastic-buffer half-full flag as a reliable one-bit phase detector and the zero-delay PLL preserving deterministic phase without adding measurable jitter—yet no auxiliary data (phase histograms at lock, metastability checks, or direct PLL additive-jitter measurements) are supplied to confirm these assumptions hold at the claimed precision.

    Authors: We agree that auxiliary measurements would provide stronger substantiation for the phase-alignment assumptions. In the revised manuscript we will add to §4: (i) phase histograms captured at FSM lock points showing the distribution of the elastic-buffer pointer difference, (ii) a brief metastability analysis of the half-full flag sampling, and (iii) direct additive-jitter measurements of the zero-delay PLL obtained with a high-bandwidth oscilloscope. These data will be presented alongside the existing synchronization results. revision: yes

  2. Referee: [Abstract, §4] Abstract and §4: the experimental results lack any statement of the number of independent trials, measurement duration, statistical error analysis, or assessment of systematic effects (temperature drift, fiber-length variation, power-supply noise), which are required to substantiate the reported sigma values and the claim of stability across power cycles.

    Authors: We concur that explicit reporting of experimental statistics and systematic-effect analysis is necessary. The revised §4 will include: the total number of independent trials and their durations, the statistical method used to compute the reported sigmas (including uncertainty on the sigma estimate), and quantitative assessments of temperature drift, fiber-length sensitivity, and power-supply noise. The power-cycle stability claim will be supported by repeated measurements with tabulated results. revision: yes

Circularity Check

0 steps flagged

Empirical engineering paper; no derivations, fits, or self-referential predictions

full rationale

The manuscript describes a hardware architecture (daisy-chain optical link, MGT elastic-buffer phase alignment, zero-delay PLL clock cleaning) and reports direct experimental measurements of synchronization sigma using CERN PicoTDC boards. No equations, parameter fits, or predictions are claimed; timing results are obtained from external instrumentation rather than derived from internal models. No self-citations appear in the provided text, and the central claims rest on measured data rather than any reduction to prior author work or internal definitions.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The paper is an engineering development paper with no free parameters fitted to data; relies on standard electronics assumptions about transceiver behavior and PLL performance.

axioms (1)
  • domain assumption Standard assumptions about the behavior of multi-gigabit transceivers and zero-delay PLLs in FPGA systems hold as described in vendor documentation.
    The alignment strategy and phase coherence rely on these components functioning without unexpected jitter or drift.

pith-pipeline@v0.9.1-grok · 5856 in / 1305 out tokens · 54277 ms · 2026-07-02T03:08:41.725096+00:00 · methodology

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Reference graph

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