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arxiv: 2606.25673 · v1 · pith:WFVTOS3Xnew · submitted 2026-06-24 · 💻 cs.AR

Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon

Enrico Zelioli , Philippe Sauter , Thomas Benz , Hannah Pochert , Luisa W\"uthrich , Beat Muheim , Frank K. G\"urkaynak , Luca Benini This is my paper

Pith reviewed 2026-06-25 19:02 UTC · model grok-4.3

classification 💻 cs.AR
keywords open-source siliconRISC-VVLSI educationdomain-specific SoC130nm PDKtapeout projectsmicrocontroller designend-to-end flow
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The pith

An open-source RISC-V platform called Croc lets students design, tape out, and test functional microcontrollers using only free EDA tools and a 130nm PDK.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper introduces Croc as a customizable RISC-V SoC platform built from open-source SystemVerilog blocks and paired with a complete open-source design flow in a 130nm open PDK. It reports on a first course in which 65 students finished 33 projects, 30 of them producing manufacturable layouts, 18 advancing to tapeout candidates, and five reaching fabrication. One baseline chip has been characterized in silicon and shows microcontroller-class operation with area, power, and performance numbers comparable to similar closed-source designs. The work aims to address the shortage of engineers skilled in domain-specific SoC design by removing licensing barriers to hands-on VLSI training.

Core claim

Croc is a highly customizable RISC-V platform integrated with open-source IP and an end-to-end open-source EDA flow in a 130nm open PDK. When used for student tapeout projects, it supports instruction-set extensions, accelerator co-processors, and custom peripherals, resulting in 33 completed projects of which 30 yielded manufacturable layouts, 18 tapeout candidates, five fabricated designs, and one baseline chip that has been successfully characterized in silicon with metrics matching those of comparable closed-source microcontroller products.

What carries the argument

Croc, the customizable RISC-V platform that carries instruction-set extensions, accelerator co-processors, and peripheral customizations through the open-source flow to silicon.

If this is right

  • Domain-specific SoCs can be built by students through instruction-set extensions, co-processors, and peripheral additions without proprietary licenses.
  • The flow produced 30 manufacturable layouts from 33 student projects and advanced 18 to tapeout.
  • Five designs reached fabrication, with one baseline chip already verified in silicon.
  • Implementation metrics of the open-source designs are presented as comparable to closed-source equivalents of similar complexity.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • If the flow scales, universities could run larger cohorts without access to expensive commercial tool licenses.
  • Success at the microcontroller level may encourage attempts at more complex domain-specific accelerators in later courses.
  • Wider adoption could shift the default training path for VLSI engineers toward open-source stacks.

Load-bearing premise

Open-source EDA tools and the 130nm PDK can produce microcontroller designs whose quality, area, power, speed, and yield match what closed-source commercial flows achieve for the same functional class.

What would settle it

A side-by-side measurement showing that the fabricated baseline chip's measured area, power consumption at a given frequency, or maximum clock speed falls more than 30 percent short of published metrics for commercial microcontrollers of similar complexity fabricated in the same or comparable process nodes.

Figures

Figures reproduced from arXiv: 2606.25673 by Beat Muheim, Enrico Zelioli, Frank K. G\"urkaynak, Hannah Pochert, Luca Benini, Luisa W\"uthrich, Philippe Sauter, Thomas Benz.

Figure 1
Figure 1. Figure 1: GDSII renders of the student layouts produced in the 2025 VLSI course with manufactured ones highlighted. [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 4
Figure 4. Figure 4: MLEM on testbed [PITH_FULL_IMAGE:figures/full_fig_p002_4.png] view at source ↗
read the original abstract

The demand for domain-specific systems-on-chip (SoCs) in artificial intelligence, robotics, and automotive systems is increasing the need for engineers with hands-on expertise on very-large-scale integration (VLSI) design from architecture specification to fabricated silicon. Yet, most VLSI courses rely on restrictively licensed electronic design automation tools and process design kits (PDKs), as well as closed-source hardware designs. We present an end-to-end open-source domain-specific SoC design and fabrication flow built around Croc, a highly customizable RISC-V platform. Built from open-source SystemVerilog intellectual property blocks and integrated with an end-to-end open-source design flow in a 130nm open PDK, Croc enables tapeout projects supporting multiple domain customization options: instruction-set extensions, accelerator co-processors, and peripherals. In our first open-source course experience using Croc, 65 students completed 33 projects, 30 of which produced manufacturable layouts. 18 designs were selected as tapeout candidates, and five were fabricated. A first baseline chip has already been successfully characterized in silicon, demonstrating microcontroller-class functionality and implementation metrics comparable to those of products with similar functional complexity completed with closed-source toolchains and PDKs.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 0 minor

Summary. The paper introduces Croc, a customizable open-source RISC-V platform for domain-specific SoC design using open SystemVerilog IP and a 130 nm open PDK. It reports results from a first course deployment in which 65 students completed 33 projects, 30 of which yielded manufacturable layouts; 18 were tapeout candidates and 5 were fabricated. A baseline chip was successfully characterized in silicon and is claimed to exhibit microcontroller-class functionality with implementation metrics comparable to closed-source commercial designs of similar complexity.

Significance. If the quantitative metrics and selection details support the comparability claim, the work would provide concrete evidence that fully open-source EDA flows and PDKs can enable end-to-end student tapeouts that reach functional silicon, directly addressing the documented shortage of hands-on VLSI training. The explicit reporting of actual fabricated and characterized silicon (rather than simulation-only results) is a notable strength.

major comments (2)
  1. [Abstract] Abstract: the central claim that the characterized baseline chip demonstrates 'implementation metrics comparable to those of products with similar functional complexity completed with closed-source toolchains and PDKs' is unsupported by any numerical values for area, power, frequency, yield, or named commercial comparators; without these data the representativeness of the open 130 nm flow cannot be evaluated.
  2. [Abstract] Abstract: the outcomes (65 students, 33 projects, 30 manufacturable layouts, 18 tapeout candidates, 5 fabricated) do not specify the selection criteria used to choose the five designs for fabrication from the 18 candidates; this omission is load-bearing for assessing whether the reported silicon success rate reflects the flow's general capability or post-selection effects.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive feedback on our manuscript. The two major comments both concern the abstract; we will revise it to address both points directly while preserving the paper's core contributions on the open-source flow and student outcomes.

read point-by-point responses

  1. Referee: [Abstract] Abstract: the central claim that the characterized baseline chip demonstrates 'implementation metrics comparable to those of products with similar functional complexity completed with closed-source toolchains and PDKs' is unsupported by any numerical values for area, power, frequency, yield, or named commercial comparators; without these data the representativeness of the open 130 nm flow cannot be evaluated.

    Authors: We agree the abstract statement is insufficiently supported as written. The revised abstract will include concrete metrics from the characterized baseline chip (area, power, frequency, and yield) together with explicit references to comparable commercial microcontroller-class designs fabricated in similar process nodes. If certain commercial numbers remain proprietary we will qualify the language accordingly rather than assert unsupported comparability. revision: yes

  2. Referee: [Abstract] Abstract: the outcomes (65 students, 33 projects, 30 manufacturable layouts, 18 tapeout candidates, 5 fabricated) do not specify the selection criteria used to choose the five designs for fabrication from the 18 candidates; this omission is load-bearing for assessing whether the reported silicon success rate reflects the flow's general capability or post-selection effects.

    Authors: We concur that the selection criteria must be stated. The revised abstract and the corresponding results section will explicitly describe the criteria applied to choose the five fabricated designs from the 18 tapeout candidates (e.g., verified functionality, layout completeness, and fabrication-slot constraints). This will clarify that the reported silicon results are not the product of undisclosed post-selection. revision: yes

Circularity Check

0 steps flagged

No significant circularity; empirical results from fabrication and measurement

full rationale

The paper reports an educational flow and empirical outcomes from 65 students producing 33 projects, with 5 fabricated chips and one characterized in silicon. No equations, fitted parameters, predictions, or derivations appear in the provided text. Central claims rest on physical silicon measurements and project counts rather than any reduction to self-defined inputs, self-citations, or ansatzes. The paper is self-contained against external benchmarks (actual tapeouts and characterization), warranting score 0 per the rules for non-derivational empirical work.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 1 invented entities

The central claim depends on the domain assumption that open-source tools and PDK can match closed-source results for microcontroller-class designs; Croc itself is the main new entity introduced without independent evidence beyond the reported course.

axioms (1)
  • domain assumption Open-source EDA tools and 130nm PDK can produce functional silicon with metrics comparable to closed-source flows for microcontroller-class SoCs.
    Invoked to support the claim that the fabricated baseline chip demonstrates comparable implementation metrics.
invented entities (1)
  • Croc RISC-V platform no independent evidence
    purpose: Highly customizable base SoC for domain-specific extensions in an educational open flow.
    New platform constructed from open IP blocks and presented as the core of the teaching flow.

pith-pipeline@v0.9.1-grok · 5774 in / 1298 out tokens · 36812 ms · 2026-06-25T19:02:03.092905+00:00 · methodology

discussion (0)

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Reference graph

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