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REVIEW 3 major objections 5 minor 9 references

An auto-scaling wide dynamic range current to frequency converter for real-time monitoring of signals in neuromorphic systems

T0 review · 3 major / 5 minor · reviewed 2026-08-14 · deepseek-v4-flash

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Pith's one-line read A compact auto-scaling converter turns picoampere-to-microampere neural currents into asynchronous spike trains with a six-decade dynamic range, letting neuromorphic chips stream their internal analog signals.

desk verdict A real auto-ranging current-to-frequency converter for neuromorphic current monitoring, linear over about five decades, but the 6-decade/pA claim needs external calibration and the β/α arithmetic is wrong. read the letter →

arxiv 1908.06545 v1 pith:WVQJZ4K2 submitted 2019-08-19 cs.ET

Ning Qiao , Giacomo Indiveri This is my paper · ORCID
classification cs.ET
keywords current-to-frequencyconverterneuromorphicVLSIreal-timecurrentmonitoringauto-scalingpulsefrequencymodulationsubthresholdCMOSsiliconneuronlog-domaincircuits
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper claims that a single compact CMOS circuit can monitor the analog currents produced by neuromorphic neuron and synapse circuits in real time, converting currents from about 10 pA to 1 µA into pulse trains whose rate is linearly proportional to the input current. The design avoids external scaling by automatically detecting the current's magnitude and switching between two integration paths, so output firing rates stay in a manageable range across six decades of input. Measured on six instances in a 180 nm process, the circuit matches circuit-simulation transistor currents and tracks the dynamics of an adaptive exponential integrate-and-fire neuron and a DPI synapse. If correct, the converter gives neuromorphic systems a low-power way to observe their own internal currents without disturbing the circuits being measured.

What carries the argument

The central object is the range-detecting current-mirror network followed by a dual-capacitor integrator. The P/N selector rectifies the input current $I_M$ to $I_U$; transistors M6–M8 copy $I_U$ to $I_O$, and M6–M10 copy it to $I_S = \beta I_O$ with $\beta = 10$. A comparator on the gate of M6 decides whether $I_M$ is below or above a programmable threshold, generating signals S1 and S2 that route either $I_O$ onto $C_1$ or $I_S$ onto $C_2$, where $C_2/C_1 = \alpha = 10$. The discriminator fires an asynchronous AER request pulse when the integrating capacitor voltage crosses the low reference voltage, and the acknowledge signal resets the integrator. Equation (1) is the governing identity: it ties the inter-spike interval directly to the monitored current, with the auto-scaling factor $\alpha/\beta$ determining which input range maps to a given output rate.

What would settle it

Inject calibrated currents below 10 pA, for example 3 pA and 5 pA, from a precision source into the converter input and count output pulses over a fixed window; the governing equation predicts a specific nonzero rate, and observing no pulses or a rate that deviates from the predicted linear relation would falsify the claimed low-current sensitivity. A second check is to compare the converter-derived current against a calibrated ammeter near the auto-scaling threshold and verify the pulse-rate continuity across the switch.

Watch

Extended reading notes

Core claim

The central discovery is an asynchronous auto-scaling current-to-frequency converter whose inter-spike interval obeys $\delta T = \beta C(V_{\mathrm{refH}} - V_{\mathrm{refL}})/(\alpha I_{\mathrm{mon}})$, so that the output pulse rate is linearly proportional to the monitored current $I_{\mathrm{mon}}$. A range detector compares the rectified input current to a threshold and selects whether to integrate the un-scaled current $I_O$ on a small capacitor $C_1$ or the scaled current $I_S = \beta I_O$ with $\beta = 10$ on a larger capacitor $C_2 = 10 C_1$, giving a total 100-fold scaling for large currents. In measurements, the circuit accurately measures currents from about 10 pA to 1 µA; currents below about 5.5 pA produce no output because of current-mirror leakage, and currents above 1 µA distort because the reset pulse becomes comparable to the inter-spike interval. Connected to an adaptive exponential integrate-and-fire neuron and a DPI synapse, the converter output reproduces the exponential decay and rise of the log-domain membrane current, demonstrating that the converted pulse train is a faithful real-time monitor of neural dynamics.

Load-bearing premise

The load-bearing premise is that the current mirrors copy the small input current to the integration branch with negligible leakage and mismatch down to picoampere levels; below about 5.5 pA this copying itself is the reason the output goes silent, so if mirror accuracy degrades, the linear mapping fails exactly where the claimed sensitivity matters most.

Editorial extensions

If this is right

  • Neuromorphic chips can monitor their internal log-domain currents on-line during experiments, without the compression artifacts introduced by voltage buffering.
  • Neuron and synapse parameters such as time constants and synaptic weights become directly readable from the inter-spike intervals of the converter's pulse train.
  • Because the output rate is kept within a limited range while the input spans six decades, the same circuit can serve both slow adaptive neural dynamics and fast transient currents without reconfiguration.
  • With a worst-case power dissipation of about 36 nW at a 100 kHz output rate, embedding one converter per monitored node in a large-scale neuromorphic system becomes practical.
  • The programmable threshold and bias voltages let designers tune the same design for different current ranges and output rates across applications.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • I infer that the 5.5 pA floor is a leakage limit of the 180 nm mirror network, not a fundamental barrier, so techniques used in femtoampere current-mode circuits could push the operational floor lower in a derivative design.
  • A testable extension is to drive the converter with a sinusoidally modulated current and measure the recovered amplitude and phase across the auto-scaling threshold; this would quantify where the finite reset pulse limits bandwidth at the high-current end.
  • The range-detection state signals S1 and S2 could be read out as an explicit scale bit, effectively doubling the bit depth of the current readout for a given output rate.
  • The same auto-scaling principle could be applied to other sensor front-ends that need wide dynamic range with limited output bandwidth, such as photodiode or electrochemical current monitors.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The paper presents a compact asynchronous current-to-frequency converter (CFC) for real-time monitoring of analog currents in neuromorphic systems. The circuit auto-detects the scale of the input current and switches between two integration paths, producing pulse-frequency-modulated output spikes whose rate is claimed to be linearly proportional to the input current. The authors derive the inter-spike interval in Eq. (1), describe the block-level and transistor-level implementation, and report measurements from six instances fabricated in a 180 nm CMOS process. Experimental results show linear conversion over a range stated as approximately 10 pA to 1 µA, with evidence of leakage below 5.5 pA and distortion above 1 µA. The paper also demonstrates real-time monitoring of silicon neuron and synapse currents. The central claim, repeated in the abstract and conclusions, is a dynamic input range of "up to 6 decades, ranging from pico-Amps to micro-Amps".

Significance. If the headline range were fully supported, this CFC would be a valuable, compact monitoring block for mixed-signal neuromorphic systems. The paper has genuine strengths: Eq. (1) is a clean standard capacitor-integration derivation; Fig. 4 shows broadly linear conversion over about five decades; the circuit is compact (150 µm × 40 µm) and low-power (about 36 nW at the maximum foreseen rate); and the neuron/synapse recordings demonstrate practical utility for real-time monitoring. However, the measured data support only about five decades (10 pA to 1 µA), not the claimed six decades from picoamperes to microamperes, and the validation at the picoampere end relies on current inferred from the CFC itself and a SPICE simulation rather than a calibrated external current source. These issues are load-bearing for the paper's central quantitative claim and need to be addressed.

major comments (3)
  1. [Abstract, Section III (Fig. 4), Conclusions] The claim of "up to 6 decades, ranging from pico-Amps to micro-Amps" is contradicted by the reported data. Section III states that the circuit "can accurately measure currents ranging from approximately 10pA to 1 µA", that "currents smaller than 5.5pA produce no effective output, mainly because of leakage issues in the current mirrors", and that "currents larger than 1µA lead to distortions". A range from 10 pA to 1 µA is five decades, and even the more optimistic 5.5 pA to 1 µA is about 5.3 decades. The 6-decade claim should be removed or replaced with an explicit statement that the demonstrated range is about five decades.
  2. [Section II, Eq. (1)] The definitions of β and α are internally inconsistent. The text first says "IS = βIO, with β<1", then later says "we set the current mirror ratio β=M10/M9 to 10, and the integration capacitor ratio α=C2/C1 to 10. So for currents larger than ... the total scaling factor is β/α=100". If β=10 and α=10, then β/α equals 1, not 100, and β=10 also contradicts the earlier β<1. Please correct the notation, the arithmetic, and the formula for the total scaling factor, because Eq. (1) is the central quantitative relation of the paper.
  3. [Section III, Fig. 5] The picoampere-end validation is not independent. The "corresponding measured current" is computed from the CFC output itself using the converter's transfer relation, and the external reference is a SPICE simulation of the same p-FET bias transistor, not a calibrated ammeter or a calibrated current source. Since the paper also reports that currents below 5.5 pA produce no output, the claim of pA-range sensitivity should be softened to "tens of picoamperes" unless a measurement with a calibrated sub-pA current source is provided.
minor comments (5)
  1. [Section II, Pulse Extender discussion] The text states "reset pulse lengths of TRST = 0.1µm are sufficiently smaller than the typical δTs produced"; the unit is almost certainly microseconds (µs), not micrometers (µm).
  2. [Section I] There is a typo: "subtreshold" should be "subthreshold".
  3. [Fig. 4 caption] The caption lists five current sweeps and the figure shows the data; consider marking the region below 10 pA where no effective output is produced, so that the figure does not misleadingly suggest a full six-decade span.
  4. [Section II, Fig. 2] The notation is inconsistent in small ways: "Vref H" and "Vref L" appear with irregular spacing, and phrases like "the current throughM13" are missing spaces. A careful formatting pass would improve readability.
  5. [Section III] The sentence "currents larger than 1µA lead to distortions, because of ... the finite pulse width of the spikes TRST" should clarify whether this upper limit depends on the chosen bias settings (e.g., the 100 nA scaling threshold) or is a fixed property of the implementation.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: Eq. (1) follows from capacitor integration physics, and the experimental validation compares CFC-derived currents to an independent SPICE simulation of the bias transistor.

full rationale

The paper's central derivation is self-contained. Eq. (1), δT = βC(VrefH − VrefL)/(αImon), is obtained directly from the circuit topology: the selected mirror ratio β, the selected capacitor ratio α, the programmed reference-voltage swing, and the capacitance determine the integration slope, so the inter-spike interval is the ratio of a fixed charge to the input current. No free parameter is fitted to the measured pulse rates and then reused to 'predict' those same rates. The experimental section converts measured pulse intervals back to currents using the same known component values, which is the normal operating principle of a current-to-frequency converter, not a circular validation. The p-FET injection current is independently checked against a SPICE simulation of the same transistor, and the observed 5.5 pA leakage floor is reported as an empirical limitation. This floor, together with the stated 10 pA to 1 µA measured range, weakens the literal '6 decades from pico-Amps to micro-Amps' claim, but that is an accuracy/overstatement issue, not circular reasoning. Self-citations are contextual: Ref. [4] supplies the neuron/synapse circuits being monitored, Ref. [7] supplies the bias generator, and Ref. [8] supplies the AdExp model; none of these is used as an unverified premise to force the converter's transfer function. The derivation does not reduce to its inputs by construction.

Assumptions & free parameters 5 free parameters · 4 assumptions · 0 invented entities

The central claim depends on hand-chosen circuit parameters (β, α, C1/C2, voltage swing, and scaling threshold) and on standard CMOS operating assumptions. No new physical entities are introduced; the blocks are conventional transistor circuits. The design parameters are engineering choices, not data-fitted quantities, but they are load-bearing for the stated conversion function.

free parameters (5)
  • β (current scaling ratio IS/IO) = stated both as β<1 and as β=M10/M9=10; text is inconsistent
    Hand-chosen ratio that determines how much current is scaled before integration for the large-current path; the contradiction in the manuscript affects the interpretation of Eq. (1).
  • α (capacitor ratio C2/C1) = 10
    Hand-chosen ratio of the two integration capacitors; combines with β to set the auto-scaling factor.
  • C1 and C2 (integration capacitors) = C1=100 fF, C2=1 pF
    Chosen capacitor values that, together with the voltage swing, set the conversion gain and output frequency range.
  • VrefH - VrefL (integrator voltage swing) = example 1 V
    Programmable voltage difference that directly multiplies the inter-spike interval in Eq. (1); it is tuned to select the desired output firing rate.
  • ISW (scaling reference threshold) = 10 nA in example; 100 nA in Fig. 5 experiment
    User-programmable threshold at which the range detector switches between the unscaled and scaled paths; must be set correctly for auto-ranging behavior.
assumptions (4)
  • domain assumption Current mirror copies are exact: IS = β·IO and IO ≈ IM after rectification, with negligible leakage and mismatch.
    Used throughout Section II to derive Eq. (1); the authors later state that leakage makes this fail below about 5.5 pA.
  • domain assumption The reset pulse duration is negligible compared to the inter-spike interval.
    Stated in Section II as the condition for linear response; the authors note it is violated for currents above about 1 µA.
  • domain assumption The SPICE simulation with the foundry transistor model accurately represents the fabricated transistor's current.
    This is the basis of the validation comparison in Fig. 5.
  • standard math Capacitor integration follows Q=CV and I=C dV/dt over the operating range.
    This is the physical basis of Eq. (1).

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Cite this review

Pith. "Pith review of An auto-scaling wide dynamic range current to frequency converter for real-time monitoring of signals in neuromorphic systems." pith.science (2026). https://pith.science/paper/WVQJZ4K2

@misc{pith2026190806545,
  author       = {Pith},
  title        = {Pith review of: An auto-scaling wide dynamic range current to frequency converter for real-time monitoring of signals in neuromorphic systems},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/WVQJZ4K2}},
  note         = {Machine review of arXiv:1908.06545}
}
read the original abstract

Neuromorphic systems typically employ current-mode circuits that model neural dynamics and produce output currents that range from few pico-Amperes to hundreds of micro-Amperes. On-line real-time monitoring of the signals produced by these circuits is crucial, for prototyping and debugging purposes, as well as for analyzing and understanding the network dynamics and computational properties. To this end, we propose a compact on-chip auto-scaling Current to Frequency Converter (CFC) for real-time monitoring of analog currents in mixed-signal/analog neuromorphic electronic systems. The proposed CFC is a self-timed asynchronous circuit that has a wide dynamic input range of up to 6 decades, ranging from pico-Amps to micro-Amps, with high current measurement sensitivity. To produce a linear output frequency response, while properly covering the wide dynamic input range, the circuit automatically detects the scale of the input current and adjusts the scale of its output firing rate accordingly. Here we describe the proposed circuit and present experimental results measured from multiple instances of the circuit, implemented using a standard 180 nm CMOS process, and interfaced to silicon neuron and synapse circuits for real-time current monitoring. We demonstrate how the circuit is suitable for measuring neural dynamics by showing the converted response properties of the chip silicon neurons and synapses as they are stimulated by input spikes.

Figures

Figures reproduced from arXiv: 1908.06545 by the authors.

Figure 1
Figure 1. Block diagram describing the architecture of proposed [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Circuit schematic of the proposed CFC. The monitored current IM is rectified as IU , mirrored as IO, and scaled down as IS. In parallel, the Range Detector circuit evaluates IM and produces the signals S1 and S2 for integrating either IO on C1 or IS on C2 by transistors M11,12,16,17. The voltage V (t) gradually decreases during the integration phase, from it’s initial value VrefH; once V (t) reaches VrefL, it trigge… view at source ↗
Figure 3
Figure 3. Die micro-photograph of the test chip with 6 [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figures from the paper (3 more)
Figure 4
Figure 4. Figure 4: CFC response (color symbols) to five linear current sweeps ( 3.2 pA to 820 pA, 26 pA to 6.5 nA, 196 pA to 50 nA, 1.57 nA to 4 µA, 12.5 nA to 3.2 µA) generated by p-FET transistors biased via an on-chip bias generator (color lines). interfaced each of the CFC blocks to …
Figure 6
Figure 6. Figure 6: Neural dynamics in monitored silicon exponential [PITH_FULL_IMAGE:figures/full_fig_p004_6.png]
Figure 7
Figure 7. Figure 7: DPI synapse current dynamics in response to input voltage spikes. (Top) input spike train. (Bottom) derived current measured from the CFC pulses. Pair Integrator (DPI) circuit [4], in response to input voltage spikes. Using these measurements it is straightforward to d…

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Works this paper leans on

9 extracted references · 9 canonical work pages

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