Typed states for the displayed outbound observations.
Source: paper_references, paper_reference_links
Paper Citation Record · LEDGER
Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation
As of 7 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 2 inbound Pith citation observations for arXiv:2407.08473.
A citation records a reference. It does not transfer a finding from one paper to another.
Coverage vector
One-hop event checks from named stored sources.
Source: scholarly_work_events, retraction_status_cache, observed 2026-08-07T06:34:17.273281+00:00
Pith citing papers itemized under the disclosed page cap.
Source: paper_references, paper_reference_links, observed 2026-08-06T15:47:16.478725Z
A source-named dated measurement, never combined with another source.
Source: pith, observed 2026-08-06T15:19:55.464670Z
Reference resolution
0 of 0 outbound references displayed
- verified exact0
- verified fuzzy0
- unresolved0
- parse uncertain0
- malformed identifier0
- metadata mismatch0
External citation measurements
No source-named external measurement is stored.
Outbound references
No outbound reference observations are available for this paper version.
Pith citing papers
Observation 70bde7e2-afaf-4939-b64b-2e0c5d52b1d5 · inbound
RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs cites this paper.
RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation
Reference 27
- Resolution
- verified exact
- local_arxiv, observed 2026-08-06T15:19:55.561303Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.
Observation cb354ab6-fc00-429b-8e3c-35e283ce1780 · inbound
TD-Interpreter: Enhancing the Understanding of Timing Diagrams with Visual-Language Learning cites this paper.
TD-Interpreter: Enhancing the Understanding of Timing Diagrams with Visual-Language Learning Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation
Reference 11
- Resolution
- unresolved
- no resolver link, observed 2026-08-06T15:47:16.478725Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.