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arxiv: 2605.18683 · v1 · pith:XX7EZSL2new · submitted 2026-05-18 · 💻 cs.DC

EPIC: Abstraction and Polymorphism of In-Network Collectives on Ethernet

Yitao Yuan , Jianglong Nie , Tianyu Bai , Ruizhe Zhou , Siyuan Cao , Xujie Fan , Yuchen Xu , Junkai Chen
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Chenqi Zhao Nengyuan Zhang Shaoke Fang Jiangyuan Chen Yuanfeng Chen Jiaqi Sun Zhan Wang Xiaohua Xu Yuchao Zhang Yang Liu Xiangrui Yang Jing Lin Xiaohe Hu Yang Li Chao Jiang Limin Xiao Weifeng Zhang Junjie Wang Wei Cheng Yazhu Lan Jianbo Dong Binzhang Fu Wenfei Wu
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Pith reviewed 2026-05-20 08:04 UTC · model grok-4.3

classification 💻 cs.DC
keywords in-network collectiveEthernet protocolabstractionpolymorphismAI accelerationnetwork hardwarecollective operationsINC
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The pith

EPIC introduces a standard-Ethernet-compatible abstraction for in-network collectives that supports polymorphic realizations across different hardware capabilities.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper proposes EPIC to enable in-network collective acceleration for AI on Ethernet by creating a unified abstraction that aligns functional boundaries with participant roles. This abstraction supports polymorphic realizations that adapt to different hardware capabilities. It solves adoption issues in the open Ethernet ecosystem through a modular design for incremental hardware development, formal verification of correctness, and a versatile resource management model. Sympathetic readers would care as this could optimize AI training and inference without needing proprietary hardware.

Core claim

EPIC (Ethernet Polymorphic In-network Collective) is an INC protocol specification and reference system built on 'Unified Abstraction, Polymorphic Realization'. It introduces an abstraction compatible with standard Ethernet that aligns functional boundaries with participant roles, while offering polymorphic realizations tailored to varying hardware capabilities. The design addresses challenges with modular evolution, formal proofs of correctness for all modes, and a unified resource management model.

What carries the argument

The unified abstraction in EPIC that aligns functional boundaries with participant roles to enable polymorphic realizations for hardware of varying capabilities.

If this is right

  • Vendors can incrementally develop hardware from simple to complex implementations without losing compatibility.
  • Formal verification confirms the correctness of all proposed polymorphic modes.
  • A unified resource management model supports a wide range of in-network collective scenarios.
  • Performance gains are realized in AI training and inference workloads.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • This abstraction could be adapted to other networking standards to broaden INC adoption.
  • Real-world deployments might reveal optimizations for specific AI model types.
  • The modular approach could template other cross-layer network protocols.

Load-bearing premise

A modular design enables an evolutionary path from simple to complex implementations allowing vendors to iterate their hardware incrementally.

What would settle it

A failure in formal verification of any polymorphic mode or the absence of performance gains in Tofino testbed experiments compared to standard Ethernet collectives would falsify the claims.

Figures

Figures reproduced from arXiv: 2605.18683 by Binzhang Fu, Chao Jiang, Chenqi Zhao, Jianbo Dong, Jianglong Nie, Jiangyuan Chen, Jiaqi Sun, Jing Lin, Junjie Wang, Junkai Chen, Limin Xiao, Nengyuan Zhang, Ruizhe Zhou, Shaoke Fang, Siyuan Cao, Tianyu Bai, Wei Cheng, Weifeng Zhang, Wenfei Wu, Xiangrui Yang, Xiaohe Hu, Xiaohua Xu, Xujie Fan, Yang Li, Yang Liu, Yazhu Lan, Yitao Yuan, Yuanfeng Chen, Yuchao Zhang, Yuchen Xu, Zhan Wang.

Figure 1
Figure 1. Figure 1: EPIC’s abstraction isolation and contention-based sharing—transforming frag￾mented resources into a flexible, programmable fabric. This approach minimizes administrative overhead while maximiz￾ing resource utilization across dynamic AI scenarios (§6). 3 EPIC OVERVIEW 3.1 Abstraction We define EPIC’s abstraction and map it to Ethernet clusters. EPIC’s realization can support 6 collective primitives. INC Tre… view at source ↗
Figure 3
Figure 3. Figure 3: EPIC Architecture 3.3 Workflow 3.3.1 System and Group Lifecycle Bootup. The lifecycle begins with component initialization: CommLib daemons launch on hosts, and IncEngine is en￾abled on switches. All instances report local states to the IncManager, which constructs the global topology and man￾ages resources (§6.1). When an application calls InitGroup(), the IncManager computes and maps a logical IncTree on… view at source ↗
Figure 4
Figure 4. Figure 4: Flow Control in CommLib [PITH_FULL_IMAGE:figures/full_fig_p005_4.png] view at source ↗
Figure 6
Figure 6. Figure 6: A pitfall in Mode￾III design age the same pre-configured routing rules and polymorphic RoCE functions, ensuring high-performance communica￾tion without the bidirectional result distribution required by AllReduce. Interaction with RoCE Flow Control and Congestion Control. EPIC’s flow control means keeping inflight data volume from overwhelming the switch buffers. The three mechanisms — EPIC flow control, Ro… view at source ↗
Figure 8
Figure 8. Figure 8: Lookup Tables in Mode-III psnStart (Recv States) arrived[N] epsn Endpoint 1 (Send States) lastAcked payload buffer Endpoint A degree buffer Pipe data pkt ACK incoming endpoints outgoing endpoints ACK iff pkt.psn ∈ [psnStart, psnStart+N) ≡ min{o.lastAcked | o∈outgoing}+1 [PITH_FULL_IMAGE:figures/full_fig_p007_8.png] view at source ↗
Figure 10
Figure 10. Figure 10: Comparison of Modes (outer is better). requires full message reception prior to processing, whereas Mode-II/III utilize packet-level (MTU) pipelining. Conse￾quently, Mode-II/III reduces end-to-end latency by approx￾imately (2𝐻 − 1) (𝑀 − 1)𝑈 /𝐵, offering advantages unless the message size 𝑆 is exceptionally large or the propagation delay 𝐿 dominates. Logic Complexity. Considering the module organization, M… view at source ↗
Figure 13
Figure 13. Figure 13: [Testbed, Tree-2-8] Collective Algorithm [PITH_FULL_IMAGE:figures/full_fig_p011_13.png] view at source ↗
Figure 12
Figure 12. Figure 12: [Testbed, Tree-2-8] AllReduce Algorithm Throughput finish normally. EPIC-III has more complex switch workflow, so its throughput is lower than EPIC-II. It is hard to make a fair performance comparison (and not the goal of emulation) among EPIC-I vs EPIC-II/III vs MPI, because their software stack differs (details in Appendix §J). Evolvability. The development of EPIC-II and III follows the modular design.… view at source ↗
Figure 14
Figure 14. Figure 14: [Testbed, Tree-2-8] Bandwidth Comple￾ments between ReduceScatter and AllGather receive for both ring-based collectives, causing bandwidth contention. Conversely, EPIC breaks this limit by exploit￾ing directional link independence. By orchestrating nodes to transmit for RS while receiving for AG (and vice versa), EPIC ensures non-overlapping directional flows. Consequently, EPIC achieves a theoretical thro… view at source ↗
Figure 15
Figure 15. Figure 15: [Packet Simulation, Tree-2-8] AllReduce Al [PITH_FULL_IMAGE:figures/full_fig_p012_15.png] view at source ↗
Figure 16
Figure 16. Figure 16: [Flow Simulation] Tail 15% JCT of Alibaba [PITH_FULL_IMAGE:figures/full_fig_p013_16.png] view at source ↗
Figure 17
Figure 17. Figure 17: EPIC in switch micro architecture Modern high-performance switches typically utilize a pipelined architecture comprising an Ingress Pipeline, a Traffic Man￾ager (TM), and an Egress Pipeline. The Ingress Pipeline per￾forms packet parsing and forwarding decisions, while the TM serves as the data plane core, managing on-chip shared memory for buffering and scheduling. The Egress Pipeline completes the proces… view at source ↗
Figure 18
Figure 18. Figure 18: Transmission Efficiency Switches operate in Store-and-Forward model but at differ￾ent granularities across modes. Following the definitions in [PITH_FULL_IMAGE:figures/full_fig_p020_18.png] view at source ↗
Figure 19
Figure 19. Figure 19: IncManager and policies [PITH_FULL_IMAGE:figures/full_fig_p021_19.png] view at source ↗
Figure 20
Figure 20. Figure 20: [Flow Simulation] JCT CDF of Trace 1 on 2048-GPU Fat-tree. 4,500 5,000 5,500 6,000 6,500 7,000 0 0.2 0.4 0.6 0.8 1 Job Completion Time (s) CDF (a) All Jobs Ring EDT Spatial Mux Temporal Mux 4,500 5,000 5,500 6,000 6,500 7,000 0.85 0.9 0.95 1 Job Completion Time (s) CDF (b) Tail 15% Jobs [PITH_FULL_IMAGE:figures/full_fig_p035_20.png] view at source ↗
Figure 23
Figure 23. Figure 23: [Flow Simulation] 8-GPU’s JCT CDF of Trace [PITH_FULL_IMAGE:figures/full_fig_p035_23.png] view at source ↗
Figure 24
Figure 24. Figure 24: [Flow Simulation] 8-GPU’s JCT CDF of Trace [PITH_FULL_IMAGE:figures/full_fig_p036_24.png] view at source ↗
read the original abstract

In-Network Collective (INC) acceleration holds immense potential for optimizing AI training and inference; however, its cross-layer nature has historically hindered investment and adoption within the open Ethernet ecosystem. To bridge this gap, we propose EPIC (Ethernet Polymorphic In-network Collective), an INC protocol specification and reference system built on the principle of "Unified Abstraction, Polymorphic Realization." EPIC introduces an abstraction compatible with standard Ethernet that aligns functional boundaries with participant roles, while offering polymorphic realizations tailored to varying hardware capabilities. We address three fundamental challenges: first, we employ a modular design that enables an evolutionary path from simple to complex implementations, allowing vendors to iterate their hardware incrementally; second, we apply formal verification methodologies to prove the correctness of all proposed polymorphic modes; and third, we develop a unified resource management model versatile enough for diverse INC scenarios. Extensive validation -- spanning model checking, packet/flow simulations, VM emulation, Tofino Testbed, and FPGA/RTL verification -- confirms EPIC's correctness, performance gain, and feasibility.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

1 major / 1 minor

Summary. The manuscript proposes EPIC (Ethernet Polymorphic In-network Collective), a protocol specification and reference system for in-network collective acceleration on Ethernet. It introduces a unified abstraction compatible with standard Ethernet that aligns functional boundaries with participant roles and supports polymorphic realizations for different hardware capabilities. The work addresses three challenges: modular design for evolutionary hardware implementation, formal verification of correctness for all modes, and a unified resource management model. Validation spans model checking, simulations, VM emulation, Tofino testbed, and FPGA/RTL verification, claiming correctness, performance gains, and feasibility.

Significance. If the central claims hold, particularly the compatibility with unmodified Ethernet and the polymorphic approach enabling incremental vendor adoption, this could facilitate broader investment and adoption of in-network collectives in the open Ethernet ecosystem for AI training and inference, addressing a historical barrier due to cross-layer nature.

major comments (1)
  1. [Abstract] Abstract: The abstract states that EPIC is 'compatible with standard Ethernet' and offers 'polymorphic realizations tailored to varying hardware capabilities', with validation including 'Tofino Testbed, and FPGA/RTL verification'. If even the basic modes require programmable switch features (as implied by the testbeds used for all modes), this contradicts the claim of compatibility with unmodified standard Ethernet hardware and the modular evolutionary path starting from simple implementations on existing vendor silicon. This is load-bearing for the central claim and requires clarification or evidence of a non-programmable basic mode.
minor comments (1)
  1. [Abstract] Abstract: The abstract mentions 'extensive validation' but does not specify quantitative performance gains or specific metrics used to confirm feasibility.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for their constructive feedback and for identifying a point that is central to the paper's claims. We address the major comment below and commit to revisions that improve clarity without altering the core technical contributions.

read point-by-point responses

  1. Referee: [Abstract] Abstract: The abstract states that EPIC is 'compatible with standard Ethernet' and offers 'polymorphic realizations tailored to varying hardware capabilities', with validation including 'Tofino Testbed, and FPGA/RTL verification'. If even the basic modes require programmable switch features (as implied by the testbeds used for all modes), this contradicts the claim of compatibility with unmodified standard Ethernet hardware and the modular evolutionary path starting from simple implementations on existing vendor silicon. This is load-bearing for the central claim and requires clarification or evidence of a non-programmable basic mode.

    Authors: We appreciate the referee highlighting this important clarification need. The EPIC abstraction is defined to be compatible with standard Ethernet by using unmodified Ethernet frame formats, standard multicast groups, and conventional switch forwarding tables for the basic mode; no programmable data-plane features are required for correct operation or role alignment in this mode. Polymorphic realizations then layer optional in-network computation on top when programmable hardware (Tofino, FPGA) is present. The listed testbeds were selected to exercise the full spectrum of modes and to provide rigorous verification of the advanced realizations, but they do not imply that the basic mode depends on programmability. We agree that the manuscript would benefit from an explicit statement of per-mode hardware requirements and a short illustrative example of the basic mode on commodity silicon. We will therefore revise the abstract, add a clarifying paragraph in Section 3, and include a table summarizing hardware prerequisites for each polymorphic variant. These changes will be incorporated in the revised manuscript. revision: yes

Circularity Check

0 steps flagged

No circularity: design proposal rests on independent specification and validation

full rationale

The paper presents EPIC as a new protocol specification and reference system based on the principle of unified abstraction with polymorphic realizations. Claims about compatibility with standard Ethernet, modular evolutionary path, formal verification, and resource management are introduced as design choices rather than derived from fitted parameters or prior self-referential results. Validation spans model checking, simulations, emulation, Tofino testbed, and FPGA/RTL, providing external checks. No equations, self-citations, or reductions to inputs by construction appear in the abstract or described structure. The derivation chain is self-contained as a proposed architecture with stated assumptions that do not presuppose the target outcomes.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 1 invented entities

The proposal rests on the assumption that formal verification can cover all polymorphic modes and that the modular structure supports incremental hardware development without additional free parameters or invented entities beyond the protocol itself.

axioms (1)
  • domain assumption Formal verification methodologies can prove the correctness of all proposed polymorphic modes.
    Stated in the abstract as one of the three fundamental challenges addressed.
invented entities (1)
  • EPIC abstraction and polymorphic realizations no independent evidence
    purpose: To provide a unified, Ethernet-compatible interface for in-network collectives with hardware-specific implementations.
    Newly defined protocol elements introduced to solve the cross-layer adoption problem.

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