Typed states for the displayed outbound observations.
Source: paper_references, paper_reference_links
Paper Citation Record · LEDGER
Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement
As of 8 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 1 inbound Pith citation observation for arXiv:2408.07886.
A citation records a reference. It does not transfer a finding from one paper to another.
Coverage vector
One-hop event checks from named stored sources.
Source: scholarly_work_events, retraction_status_cache, observed 2026-08-08T06:32:00.761636+00:00
Pith citing papers itemized under the disclosed page cap.
Source: paper_references, paper_reference_links, observed 2026-08-06T14:21:43.862210Z
A source-named dated measurement, never combined with another source.
Source: pith, observed 2026-08-06T14:21:43.927541Z
Reference resolution
0 of 0 outbound references displayed
- verified exact0
- verified fuzzy0
- unresolved0
- parse uncertain0
- malformed identifier0
- metadata mismatch0
External citation measurements
No source-named external measurement is stored.
Outbound references
No outbound reference observations are available for this paper version.
Pith citing papers
Observation ad4f67c7-4b67-4640-9f61-9a75084f34d4 · inbound
MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization cites this paper.
MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement
Reference 19
- Resolution
- verified exact
- local_arxiv, observed 2026-08-06T14:21:43.931880Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.