Enabling Efficient Hardware Acceleration of Hybrid Vision Transformer (ViT) Networks at the Edge

Joren Dumoulin; Marian Verhelst; Pouya Houshmand; Vikram Jain

REVIEW 3 major objections 5 minor 25 references

Enabling Efficient Hardware Acceleration of Hybrid Vision Transformer (ViT) Networks at the Edge

T0 review · 3 major / 5 minor · reviewed 2026-08-06 · deepseek-v4-flash

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Pith's one-line read This paper claims that hybrid vision transformers can be efficiently accelerated at the edge by a configurable processing array, pixelwise loop ordering, and inverted-bottleneck layer fusion, reporting 731.1 FPS/W and 1.39 TOPS/W on a…

desk verdict A solid, open-source hybrid-ViT accelerator with plausible architecture, but the headline 731.1 FPS/W almost certainly excludes DRAM power and should be read as a core-only number. read the letter →

arxiv 2507.14651 v1 pith:Y534YEAI submitted 2025-07-19 cs.AR

Joren Dumoulin , Pouya Houshmand , Vikram Jain , Marian Verhelst This is my paper · ORCID

classification cs.AR

keywords hybridvisiontransformerhardwareacceleratorlayerfusioninvertedbottleneckpixelwiselooporderingedgeinferenceenergyefficiencydepthwiseconvolution

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper is trying to establish that hybrid vision transformers—networks that mix convolutional layers with self-attention and normalization—can be accelerated at edge-level power, despite their diversity of layer types and large intermediate tensors. It proposes three coordinated hardware-scheduling innovations: a configurable 16x16 processing array that switches between two spatial dataflows, a pixelwise temporal loop order that absorbs layer normalization and softmax into the preceding computation, and a layer-fusion scheme that avoids storing the expanded intermediate feature map of inverted bottlenecks in off-chip DRAM. The synthesized accelerator is reported to run the hybrid benchmark network EdgeNeXt-S at 13.16 FPS, 18.4 mW, and 731.1 FPS/W, with a peak efficiency of 1.39 TOPS/W at 25.6 GMACs/s. If those numbers hold on real silicon, the work would show that hybrid ViT workloads can be handled efficiently at the edge, not just CNNs.

What carries the argument

Three mechanisms carry the argument. First, a reconfigurable processing array with two spatial dataflows—C|K for dense pointwise/GeMM operations and C|FX for depthwise convolutions—so that each layer type receives a matching parallel mapping with little area overhead. Second, a pixelwise temporal loop ordering that iterates over output pixels while producing all channels at once, so a small line buffer holds the data needed to compute layer statistics and apply layer normalization or softmax before writing back. Third, a layer-fusion schedule that tiles the intermediate feature map of an inverted bottleneck, reuses each produced tile immediately for partial output accumulation, and discards it, thereby keeping the expanded intermediate tensor on-chip instead of round-tripping it through DRAM.

What would settle it

Fabricate the chip and measure total power, DRAM transfer energy, and network FPS while running EdgeNeXt-S at 8-bit precision; if the measured network efficiency is far below 731.1 FPS/W, or the DRAM energy fraction differs substantially from the 52% the model assumes, then the layer-fusion saving and headline efficiency would not survive on real hardware.

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Extended reading notes

Core claim

The paper's central claim is that hybrid vision transformers can be made edge-deployable by co-designing spatial dataflow, temporal loop ordering, and cross-layer scheduling specifically for their mixed layer types. The author argues that a configurable 16x16 processing array alternating between C|K and C|FX spatial mappings handles both dense matrix-like operations and depthwise convolutions efficiently; that a pixelwise temporal loop order lets layer normalization and softmax be computed in-line with the preceding layer; and that fusing the two pointwise convolutions of an inverted bottleneck with tiled depth-first execution eliminates the need to write the expanded intermediate activation to DRAM. Synthesized in 28nm CMOS, the design is reported to reach 1.39 TOPS/W peak, 25.6 GMACs/s, and 731.1 FPS/W on EdgeNeXt-S, with a 37.6% total energy reduction attributed to the layer-fusion mechanism alone.

Load-bearing premise

The headline efficiency and the 37.6% energy saving come from post-synthesis power simulation plus an energy model that assumes 100 pJ/byte for DRAM access, not from a fabricated, measured chip; if that DRAM energy estimate is too high, the real silicon benefits would be proportionally smaller.

Editorial extensions

If this is right

The accelerator can execute every layer type in EdgeNeXt-S—regular and pointwise convolution, depthwise convolution, matrix multiply, layer normalization, and softmax—on a single configurable array without a separate ViT coprocessor.
Fusing the expanded intermediate tensor of inverted bottlenecks reduces DRAM traffic enough that the total system energy for the benchmark network drops by 37.6%, suggesting that data movement, not compute, dominates hybrid ViT energy.
Pixelwise temporal ordering lets normalization and softmax be folded into the preceding layer's computation, removing their latency and energy overhead even though their operation counts are small.
At 13.16 FPS and 18.4 mW, the synthesized design delivers 731.1 FPS/W at 78.8% ImageNet top-1 accuracy on EdgeNeXt-S, a combination no prior published accelerator reports for a hybrid ViT.
The parameterized implementation, with configurable PE dimensions, bus widths, memory sizes, and depthwise support, provides a template for customizing the design to other hybrid ViT models.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

The tiled depth-first fusion recipe should transfer to any two-layer contraction-expansion structure whose intermediate map exceeds SRAM capacity, including MobileNet-family bottlenecks, not only vision transformers.
The pixelwise loop ordering implies the architecture can stream activations nearly online, which could enable future extensions like per-tile dynamic quantization or input-dependent early exit without an extra pass over the feature map.
Because the energy savings rely on a post-synthesis power model with a fixed 100 pJ/byte DRAM assumption, measured silicon with a different DRAM energy fraction would recalibrate the headline 37.6% saving; the fusion approach itself would likely survive, but the magnitude would shift.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Short version: the reader's conditional verdict is right, and the stress-test concern holds up. The paper is a credible architecture contribution — configurable C|(K or FX) array, pixelwise loop ordering to fuse normalization/softmax, and inverted-bottleneck layer fusion — all packaged in an open-source, synthesized 28nm implementation. That is real and useful, especially for edge AI researchers who need to run hybrid ViTs without buying a server-class accelerator.

What is new: the specific combination of dataflows and fusions targeting EdgeNeXt-S, backed by a parameterized RTL release on GitHub. The peak 1.39 TOPS/W at 25.6 GMACs/s is internally consistent for a 16x16 8-bit array at 100 MHz, and the area breakdown (1.48 mm2, 1.1% overhead for reconfigurability) is believable. Credit where due: they shipped code, they used a reasonable DSE tool, and they state their DRAM energy assumption clearly.

Soft spots, in proportion. First, the 731.1 FPS/W headline is computed as 13.16 FPS / 18.4 mW, where 18.4 mW appears to be post-synthesis core power only. The paper's own ZigZag model says DRAM is 52% of baseline total energy and fusion cuts total energy by 37.6%; adding the fused-design DRAM energy under that model raises average power to roughly 24 mW and drops the headline to about 550 FPS/W. That is not a fatal blow, but the abstract and Table I present the core-only number as the headline, and Table I mixes this simulated core-only result with measured system power from other chips. That is an unfair comparison and should be fixed.

Second, the 18% latency saving and 37.6% energy reduction come from ZigZag, a tool several authors co-developed, and are evaluated against the authors' own baseline. They do not come from RTL simulation or silicon. This is a common DSE pattern, but it means those improvement numbers are model outputs, not measurements. The open-source release helps, but the gap between ZigZag and RTL is not quantified.

The citation pattern is honest and the related work is adequately covered. No invented entities, no hidden parameters beyond the tile sizes and DRAM constant the paper discloses.

Who this is for: hardware architects working on edge transformers, especially in the Verhelst group. A serious referee should engage with it, mainly to push for a fair power basis and a ZigZag-to-RTL sanity check. It deserves peer review, not desk rejection.

Referee Report

3 major / 5 minor

Summary. The paper presents a hardware accelerator architecture for hybrid vision transformer (ViT) networks, targeting the EdgeNeXt-S model. Three contributions are proposed: (i) a reconfigurable PE array that supports both standard convolution/GeMM dataflows and a depthwise-convolution dataflow, (ii) a pixelwise temporal loop ordering that enables fusion of normalization and softmax layers with adjacent compute layers, and (iii) a layer-fusion scheme for inverted bottleneck structures that reduces off-chip DRAM traffic. The accelerator is synthesized in TSMC 28HPC+, yielding a 1.48 mm2 core, a peak efficiency of 1.39 TOPS/W at 25.6 GMACs/s, and a claimed full-network rate of 13.16 FPS at 18.4 mW, corresponding to 731.1 FPS/W. The paper also reports an 18% latency saving and a 37.6% energy reduction from the proposed scheduling optimizations, both obtained from the ZigZag design-space exploration tool.

Significance. If the efficiency and system-level claims hold, this would be a valuable step toward hardware that covers the layer diversity of hybrid CNN/ViT networks in a single programmable accelerator. The work has concrete strengths: it provides an open-source, parameterized RTL implementation; it reports actual synthesis results in a modern technology; it explicitly addresses depthwise convolutions, LayerNorm, Softmax, and inverted-bottleneck memory traffic, which are often neglected in CNN accelerators; and it demonstrates the applicability of a dataflow DSE to a full hybrid network rather than to isolated layers. The significance is tempered, however, by the fact that the headline 731.1 FPS/W and the energy-reduction percentages depend on assumptions that are not fully disclosed or validated, and by the comparison of synthesized core-only power with measured system power from other chips.

major comments (3)

[Section V-D and Table I] The headline network efficiency of 731.1 FPS/W is computed as 13.16 FPS divided by 18.4 mW, where the 18.4 mW appears to be the on-chip power obtained from synthesis/power simulation. However, Section IV and Fig. 5 state that DRAM accesses account for up to 52% of total baseline energy and that the proposed layer fusion reduces total system energy by 37.6%. This means the paper's own model treats DRAM energy as a first-order component. If the 18.4 mW denominator excludes off-chip DRAM power, then 731.1 FPS/W is not a system-level efficiency, and Table I's comparison with measured chips from other works is apples-to-oranges. Please state explicitly whether DRAM energy is included in the FPS/W calculation; if it is not, recalculate the efficiency using the paper's own 100 pJ/byte DRAM model, report the corrected number, and adjust the abstract, conclusion, and Table I accordingly.
[Section II and Fig. 3] The 18% latency saving attributed to the reconfigurable C|(K∨FX) dataflow is a ZigZag model output on a high-level architecture template, not a measurement from the synthesized RTL or from the implemented accelerator. Likewise, the 13.16 FPS network throughput appears to derive from modeled cycle counts rather than from RTL simulation. These are useful design-space results, but they should be clearly labeled as model estimates, and the paper should report any RTL-level cycle-accurate validation that was performed. Without this distinction, the reader cannot tell which contributions are demonstrated in hardware and which are predicted by the authors' own simulation framework.
[Section IV and Fig. 5] The central energy-saving claim of 37.6% total system energy reduction depends on the assumed 100 pJ/byte DRAM access cost and on the ZigZag tile-size optimization for t1 and o1. The manuscript does not report the optimized tile sizes, the resulting DRAM traffic reduction in bytes, or a sensitivity analysis of the energy saving to the DRAM energy constant. Since DRAM energy dominates the baseline, the magnitude of the claimed benefit is highly sensitive to this assumption. Please provide the tile sizes, the DRAM traffic before and after fusion, and a sensitivity sweep (for example, 20 to 200 pJ/byte) so that the robustness of the 37.6% figure can be assessed.

minor comments (5)

[Abstract and Section V-D] The paper says the accelerator is 'implemented in 28nm CMOS,' but the results are from synthesis and power simulation, not from a fabricated chip. Please use 'synthesized in 28nm HPC+' or 'implementation target' to avoid overstating the results.
[Table I] The formatting of Table I is garbled: the 'Power Cons. (mW)' row contains entries like '3.2 -', '125.8 0.83', and '18.4 8700' that are ambiguous. Please reformat the table so that each column corresponds clearly to one prior work, with units and measurement conditions (fabricated vs. synthesized, core-only vs. full system) listed explicitly.
[Fig. 8] The normalized contributions in Fig. 8 should state clearly what the baseline is (presumably the fixed-dataflow, un-fused ZigZag mapping) and whether the energy and latency bars come from ZigZag estimates, power simulation, or RTL simulation.
[Section II] The notation C|(K∨FX) and C|K is introduced without defining the ∨ operator or the role of the vertical bar. Please define the spatial-mapping notation precisely, or add a reference where it is defined.
[Listing 1 and Section III] The loop indices in Listing 1 start at 1, but the paper elsewhere uses zero-based indexing (e.g., X[ox][oy][c] with ox, oy from 0). Please harmonize the indexing convention or state the range explicitly.

Circularity Check

0 steps flagged · score 2.0 of 10

No circular derivation; peak efficiency is from synthesis, and ZigZag-based energy estimates are model outputs rather than fitted inputs.

full rationale

The central hardware result (1.39 TOPS/W at 25.6 GMACs/s, 13.16 FPS at 18.4 mW, 731.1 FPS/W) is obtained from post-synthesis simulation in TSMC 28HPC+ (Section V-D) and is not derived from a parameter fitted to the paper's own claims. The scheduling-optimization numbers (18% latency savings, 52% DRAM energy share, 63.6% of DRAM transfers, 37.6% system-energy reduction) are generated by running ZigZag [25], a general DSE tool co-authored by three of the present authors. This is a genuine self-citation in the evaluation loop, but it is not a circular derivation: the DRAM energy assumption (100 pJ/byte) and the hardware template are stated inputs, and the reported energy/latency numbers are computed outputs of that model, not quantities the model was defined to reproduce. There is no equation in which a predicted quantity collapses into an input by construction, and no fitted parameter is renamed as a prediction. The possible exclusion of off-chip DRAM power from the 18.4 mW FPS/W denominator is a metric-consistency/correctness issue, not a circularity. Score 2 reflects the presence of a same-author tool in the evaluation loop while the main implementation claim stands on independent synthesis and external comparison.

Assumptions & free parameters 2 free parameters · 3 assumptions · 0 invented entities

The fusion gains depend on the undisclosed tile sizes chosen by ZigZag search and on the assumed 100 pJ/byte DRAM access cost. The accuracy number relies on a single quantized network run, and the ZigZag model is an in-house tool. No invented entities are introduced.

free parameters (2)

Layer fusion tile sizes t1 and o1 = not reported
Section IV states the tile sizes are optimized using ZigZag DSE, but the chosen values are not given in the text, which limits independent evaluation of the fusion tradeoff.
DRAM access energy constant = 100 pJ/byte
Chosen as the DRAM access cost estimate in Section IV; it directly feeds the 37.6% energy saving calculation and is not measured for this design.

assumptions (3)

domain assumption 8-bit quantization of EdgeNeXt-S preserves 78.8% top-1 accuracy
Table I reports accuracy, but the paper does not describe quantization methodology or accuracy loss analysis beyond the single reported number.
domain assumption ZigZag energy/latency model accurately predicts the synthesized hardware
The 18% latency saving and 37.6% energy reduction are computed by ZigZag, and the paper does not compare ZigZag estimates with RTL simulation results.
domain assumption EdgeNeXt-S is representative of hybrid ViTs
The paper generalizes its conclusions to a class of hybrid networks from a single benchmark model.

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Cite this review

Pith. "Pith review of Enabling Efficient Hardware Acceleration of Hybrid Vision Transformer (ViT) Networks at the Edge." pith.science (2026). https://pith.science/paper/Y534YEAI

@misc{pith2026250714651,
  author       = {Pith},
  title        = {Pith review of: Enabling Efficient Hardware Acceleration of Hybrid Vision Transformer (ViT) Networks at the Edge},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/Y534YEAI}},
  note         = {Machine review of arXiv:2507.14651}
}

read the original abstract

Hybrid vision transformers combine the elements of conventional neural networks (NN) and vision transformers (ViT) to enable lightweight and accurate detection. However, several challenges remain for their efficient deployment on resource-constrained edge devices. The hybrid models suffer from a widely diverse set of NN layer types and large intermediate data tensors, hampering efficient hardware acceleration. To enable their execution at the edge, this paper proposes innovations across the hardware-scheduling stack: a.) At the lowest level, a configurable PE array supports all hybrid ViT layer types; b.) temporal loop re-ordering within one layer, enabling hardware support for normalization and softmax layers, minimizing on-chip data transfers; c.) further scheduling optimization employs layer fusion across inverted bottleneck layers to drastically reduce off-chip memory transfers. The resulting accelerator is implemented in 28nm CMOS, achieving a peak energy efficiency of 1.39 TOPS/W at 25.6 GMACs/s.

Figures

Figures reproduced from arXiv: 2507.14651 by the authors.

**Figure 2.** Diagram of the EdgeNeXt [11] network, consisting of downsampling [PITH_FULL_IMAGE:figures/full_fig_p001_2.png] view at source ↗

**Figure 3.** Results of the design space exploration experiments. The architectures considered use a PE array with dimensions 16 [PITH_FULL_IMAGE:figures/full_fig_p002_3.png] view at source ↗

Figures from the paper (4 more)

**Figure 4.** Figure 4: The inverted bottleneck structure (top) and a visualization of the layer [PITH_FULL_IMAGE:figures/full_fig_p003_4.png]

**Figure 5.** Figure 5: Estimated layer fusion gains using a DRAM access cost of 100 pJ/byte. [PITH_FULL_IMAGE:figures/full_fig_p003_5.png]

**Figure 7.** Figure 7: Area breakdown (left) and Power breakdown for the computation of [PITH_FULL_IMAGE:figures/full_fig_p004_7.png]

**Figure 8.** Figure 8: Normalized contributions of the proposed optimizations on system [PITH_FULL_IMAGE:figures/full_fig_p004_8.png]

Discussion (0). Continue with ORCID to comment.

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