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REVIEW 4 major objections 5 minor 34 references

Toward Intelligent Electronic-Photonic Design Automation for Large-Scale Photonic Integrated Circuits: from Device Inverse Design to Physical Layout Generation

T0 review · 4 major / 5 minor · reviewed 2026-08-06 · deepseek-v4-flash

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Pith's one-line read PoLaRIS claims a single automated flow from photonic device inverse design to DRV-free physical layout.

desk verdict A well-written integration overview of the authors' own prior tools, but the central DRV-free layout claim is asserted rather than demonstrated — send it back until a benchmark is provided. read the letter →

arxiv 2507.22301 v1 pith:ZHKGQOC6 submitted 2025-07-30 cs.ET

Hongjian Zhou , Pingchuan Ma , Jiaqi Gu This is my paper · ORCID
classification cs.ET
keywords photonicintegratedcircuitsdesignautomationinverseplacementandroutingfabrication-awareoptimizationcurvywaveguidemachinelearningforphotonicselectronic-photonicco-design
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

PoLaRIS is a proposed end-to-end design automation framework for photonic integrated circuits, spanning device-level inverse design and system-level physical layout. The paper claims that by chaining a fabrication-aware inverse design engine (BOSON-1 and MAPS) with a routing-informed placer (Apollo) and a curvy-aware router (LiDAR), designers can automatically obtain design-rule-clean, performance-optimized layouts without manual layout work. The motivation is that current PIC design, which integrates hundreds to thousands of components, still relies on manual, script-bound, and error-prone steps. If the framework delivers what it claims, it would shorten design cycles, lower the expertise barrier, and enable scalable photonic systems.

What carries the argument

The central object is the PoLaRIS framework itself, whose two halves are PoLaRIS-InvDes and PoLaRIS-PnR. The device half is carried by BOSON-1, a fabrication-aware stochastic inverse design optimizer that embeds differentiable lithography and etching models and uses adaptive variation-aware sampling to cut simulation cost from exponential to linear, together with MAPS, a modular AI-augmented infrastructure that links multi-fidelity data generation and surrogate training to adjoint optimization. The layout half is carried by Apollo, a GPU-accelerated analytical placer that uses an asymmetric bending-aware wirelength function (cosWA) and a Blockwise Adaptive Barzilai-Borwein step size to produce routable placement, and LiDAR, a curvy-aware A* detailed router that enforces minimum bend radius and supports dynamic waveguide crossing insertion. The work these components do is to make the full flow correct-by-construction: the inverse design stage targets manufacturable devices, and the placement and routing stage targets legal, low-loss layouts.

What would settle it

Run PoLaRIS end-to-end on a representative large-scale PIC benchmark and check the produced GDS-II layout against a foundry design rule checker; finding any design rule violation, or measuring optical insertion loss significantly worse than the routed design predicts, would refute the central claim.

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Extended reading notes

Core claim

The paper's central claim is that the separate stages of photonic design—device optimization and physical layout—can be unified into a single toolflow, PoLaRIS, that generates design rule violation (DRV)-free and performance-optimized layouts automatically. It asserts that the combination of BOSON-1's fabrication-aware stochastic inverse design, MAPS's AI-augmented optimization, Apollo's routing-informed placement, and LiDAR's curvy-aware detailed routing makes the end-to-end flow practical for large-scale PICs. The paper further states that PoLaRIS-PnR, the placement-and-routing half, is the first open-source PIC layout generation toolflow. The emphasis is on integration: each component has been published separately, and PoLaRIS is the claim that they work together to automate what has been a manual, hierarchical design process.

Load-bearing premise

The load-bearing premise is that the four separately built tools still work correctly when chained together, so the combined flow can truly turn a component specification into a clean, manufacturable photonic layout.

Editorial extensions

If this is right

  • A designer could go from device specifications and a netlist directly to a correct-by-construction GDS-II layout, removing manual layout drafting and iteration.
  • Inverse-designed devices would become deployable rather than academic, because fabrication variations are modeled during optimization rather than checked afterward.
  • Layout generation for PICs with hundreds to thousands of components would scale past the manual design bottleneck, lowering the barrier for non-specialists.
  • An open-source, end-to-end PIC layout flow would enable reproducible comparisons across future placement and routing research.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The strongest test of the framework is integration itself: because each component was validated separately, an end-to-end run on a single benchmark would be more informative than the component-level results.
  • If the flow matures, the next design bottleneck shifts to front-end architecture and schematic design, so differentiable circuit simulators and photonic-electronic co-design become the natural next targets.
  • The single-layer waveguide assumption may limit the framework on future multi-layer and 3D platforms, where bend and crossing constraints change qualitatively.
  • A practical way to probe the open-source claim is to check whether the released code reproduces the paper's layouts on the disclosed benchmarks.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 5 minor

Summary. The paper proposes PoLaRIS, a two-part electronic-photonic design automation framework that combines device-level inverse design (BOSON-1 and MAPS) with system-level placement and routing (Apollo and LiDAR). The abstract claims that PoLaRIS 'enables the automated generation of design rule violation (DRV)-free and performance-optimized layouts' and that PoLaRIS-PnR is 'the first open-source PIC layout generation toolflow.' The body of the paper provides qualitative descriptions of each component, references to the authors' prior publications, and one illustrative figure of example layouts. No end-to-end experiment, measured quantity, DRC report, optical simulation result, runtime comparison, or code repository is included.

Significance. If the integration worked as claimed, PoLaRIS would be a useful contribution to PIC design automation, because it addresses an important bottleneck: bridging device-level inverse design with large-scale physical layout generation. The paper's strengths are its clear articulation of the design challenges, the sensible decomposition of the toolflow into inverse design and placement/routing, and the fact that the four components appear to have had substantive validation in their original conference publications. However, the manuscript itself provides no evidence for the integration-level claim. There is no reproducible end-to-end benchmark, no DRV statistics, no insertion-loss numbers, no comparison against a manual or prior-art baseline, and no open-source release information. The central assertions therefore remain unsupported by the evidence in this paper.

major comments (4)
  1. [Abstract; Section 4.2; Figure 8] The central claim that PoLaRIS 'enables the automated generation of DRV-free and performance-optimized layouts' is not supported by any experiment or measurement in the manuscript. Figure 8 shows example layouts but omits scale bars, DRV counts, insertion-loss values, routing runtimes, and any manual or prior-work baseline. Section 5 states that 'the successful generation of complex, DRV-free layouts demonstrates a pivotal step' but no such demonstration appears in the paper. A reproducible end-to-end benchmark, from netlist through placement and routing to a foundry-PDK DRC report and optical-loss simulation, is required before this claim can be evaluated.
  2. [Section 4.2] The claim that PoLaRIS-PnR 'enables the first open-source PIC layout generation toolflow' is unverifiable as stated: no repository URL, license, version identifier, or installation instructions are provided. Given that open-source PIC layout tools such as gdsfactory already exist, the 'first' claim needs precise scoping and supporting evidence, or it should be removed.
  3. [Section 4.1] The integration-level assumption for PoLaRIS-InvDes is load-bearing but untested: the paper asserts that chaining BOSON-1 and MAPS yields scalable, fabrication-robust inverse design, relying entirely on citations to prior DATE publications. In particular, the accuracy of the differentiable lithography and etching models and the reliability of MAPS surrogate gradients inside the optimization loop are not validated in this manuscript. If either assumption fails, the device-level component of the claimed framework does not deliver what the abstract promises.
  4. [Section 4.2; Section 5] The 'DRV-free' claim is ambiguous in scope. LiDAR's legality appears to be limited to waveguide routing rules such as bending radius, spacing, crossing conditions, and port orientation. The paper does not show that device-level DRC, electrical routing, thermal constraints, or layouts of BOSON-1/MAPS-generated components are jointly verified in the integrated flow. Without a complete DRC report on a full PoLaRIS-generated layout, the conclusion in Section 5 overstates what is demonstrated.
minor comments (5)
  1. [Throughout] There are multiple typographical errors, including 'overlookcritical' (Section 2), 'co-directionalports' (Section 4.2), and 're-defined' (Section 3), which should be corrected.
  2. [Section 4.2] The 'cosWA function' is named but never defined or given a formula; please provide its mathematical form or a precise reference to the original Apollo paper.
  3. [References] Several references are duplicated: [16] and [22] are the same work, [17] and [23] are the same work, and [19] and [24] are the same work. Also, reference [32] lists the first author as 'Mal, P.' while the text uses 'Ma, P.'; please make the citation consistent.
  4. [Figure 8] The figure has three panels with labels such as 'High crossing density' and 'Re-usable net routing' but no legend or explanation of the design examples, making it difficult to assess what the visualized layouts demonstrate.
  5. [Section 4.2] The statement 'we extend LiDAR with a hierarchical routing framework' is new relative to the cited LiDAR work but is not described. Please clarify what is original to this manuscript versus what is reported in reference [35].

Circularity Check

2 steps flagged · score 8.0 of 10

PoLaRIS's central DRV-free, performance-optimized layout claim is asserted from the authors' own prior components, with no end-to-end result in this manuscript.

  1. self citation load bearing [Section 4.2 (PoLaRIS-PnR), citing Refs. [33]-[35]]
    "PoLaRIS-PnR is formed by integrating a placer Apollo33 and a router LiDAR34,35 to achieve end-to-end layout generation for PICs. ... By integratingApolloand LiDAR, PoLaRIS-PnR enables the first open-source PIC layout generation toolflow."

    The paper's central claim—automated DRV-free, performance-optimized layout generation—is not demonstrated with any end-to-end experiment, DRC report, insertion-loss metric, or baseline comparison in this manuscript. The only support offered is Refs. [33]-[35], which are prior papers by the same authors. Section 4.2 concatenates the advertised guarantees of Apollo and LiDAR, and Section 5 then re-states those guarantees as a demonstrated result, so the conclusion reduces to the cited prior claims rather than to any evidence in this paper.

  2. self citation load bearing [Section 5 (Conclusion)]
    "The successful generation of complex, DRV-free layouts demonstrates a pivotal step toward robust and scalable PIC design automation."

    This sentence is the paper's conclusion, but 'successful generation of complex, DRV-free layouts' is not derived from any experiment or metric reported here. It is exactly the abstract's promise, supported only by the earlier references to Apollo and LiDAR [33]-[35], all of which are the authors' own publications. The conclusion therefore assumes the very capability the abstract claims to enable, making the central claim circular with respect to the self-citation chain.

full rationale

PoLaRIS is presented as a unification of four previously published components—BOSON-1 [31], MAPS [32], Apollo [33], and LiDAR [34,35]—all authored or co-authored by the present authors. The paper contains no end-to-end benchmark of the integrated PoLaRIS flow: no generated GDS with DRV counts, no insertion-loss numbers, no comparison to manual layouts, and no verification that chaining the components preserves their individual guarantees. The abstract and conclusion both assert that PoLaRIS 'enables the automated generation of design rule violation (DRV)-free and performance-optimized layouts,' but the only evidence cited for this capability is the authors' own prior publications. This is a load-bearing self-citation chain: the integrated system's advertised output is exactly the conjunction of the cited components' advertised outputs. Even if each component was validated in its own paper, the present manuscript provides no independent demonstration that the integrated toolflow works as claimed, so the conclusion restates the input rather than establishing a new result. No equation-level reduction exists because the paper contains no new equations; the circularity is at the level of the framework's central claim. Score 8 reflects that the central claim is forced by a self-citation chain rather than by demonstration or derivation.

Assumptions & free parameters 0 free parameters · 5 assumptions · 2 invented entities

The paper introduces no new numerically fitted constants; its claims depend on the validity of previously published tools and on domain assumptions about silicon photonics. The axioms above capture the unverified dependencies that the central claim rests on.

assumptions (5)
  • standard math Adjoint gradients can be obtained from two forward electromagnetic simulations.
    Standard adjoint method, invoked in Section 3.1.1 and foundational for BOSON-1.
  • domain assumption Silicon photonic layouts are single-layer, with minimum bend radii of 5 to 10 micrometers and 90 degree crossings.
    Platform-specific constraints assumed throughout Section 3.1.2 and used by Apollo and LiDAR.
  • ad hoc to paper Differentiable lithography and etching models in BOSON-1 accurately represent factory fabrication variations.
    Section 4.1 asserts these models are embedded in the optimization loop, but no equations or calibration data are given.
  • ad hoc to paper MAPS-trained surrogate models provide accurate and reliable gradients when used inside inverse design.
    The paper itself notes existing surrogates frequently fail to provide reliable gradients, then asserts MAPS solves this without presenting evidence in this manuscript.
  • ad hoc to paper Apollo and LiDAR produce DRV-free, performance-optimized layouts when run in sequence.
    Section 4.2 states this as the outcome of integration but reports no end-to-end benchmark.
invented entities (2)
  • PoLaRIS
    purpose: Umbrella framework uniting device-level inverse design and system-level layout generation.
    Introduced in this paper as the contribution, but no code, benchmark, or falsifiable handle is provided.
  • cosWA function
    purpose: Asymmetric bending-aware wirelength model in the Apollo placer.
    Mentioned by name in Section 4.2 without an equation or evaluation.

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Cite this review

Pith. "Pith review of Toward Intelligent Electronic-Photonic Design Automation for Large-Scale Photonic Integrated Circuits: from Device Inverse Design to Physical Layout Generation." pith.science (2026). https://pith.science/paper/ZHKGQOC6

@misc{pith2026250722301,
  author       = {Pith},
  title        = {Pith review of: Toward Intelligent Electronic-Photonic Design Automation for Large-Scale Photonic Integrated Circuits: from Device Inverse Design to Physical Layout Generation},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/ZHKGQOC6}},
  note         = {Machine review of arXiv:2507.22301}
}
read the original abstract

Photonic Integrated Circuits (PICs) offer tremendous advantages in bandwidth, parallelism, and energy efficiency, making them essential for emerging applications in artificial intelligence (AI), high-performance computing (HPC), sensing, and communications. However, the design of modern PICs, which now integrate hundreds to thousands of components, remains largely manual, resulting in inefficiency, poor scalability, and susceptibility to errors. To address these challenges, we propose PoLaRIS, a comprehensive Intelligent Electronic-Photonic Design Automation (EPDA) framework that spans both device-level synthesis and system-level physical layout. PoLaRIS combines a robust, fabrication-aware inverse design engine with a routing-informed placement and curvy-aware detailed router, enabling the automated generation of design rule violation (DRV)-free and performance-optimized layouts. By unifying physics-driven optimization with machine learning and domain-specific algorithms, PoLaRIS significantly accelerates PIC development, lowers design barriers, and lays the groundwork for scalable photonic system design automation.

Figures

Figures reproduced from arXiv: 2507.22301 by the authors.

Figure 1
Figure 1. Simplified PIC design flow and example automation toolkits and foundry vendors. [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Inverse design, as a high-dimensional and non-convex optimization problem, faces three key challenges: [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. (a) From design pattern to device implementation, there are multiple sources of variations (b) Exhaus [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figures from the paper (5 more)
Figure 4
Figure 4. Figure 4: Advanced optimization algorithms ensure better optimality and convergence in photonic device inverse [PITH_FULL_IMAGE:figures/full_fig_p005_4.png]
Figure 5
Figure 5. Figure 5: Illustration of AI-assisted photonic device simulation and inverse design infrastructure [PITH_FULL_IMAGE:figures/full_fig_p006_5.png]
Figure 6
Figure 6. Figure 6: Challenges of the automated PIC placement. [PITH_FULL_IMAGE:figures/full_fig_p006_6.png]
Figure 7
Figure 7. Figure 7: Proper placement constraints ensure high PIC layout quality. [PITH_FULL_IMAGE:figures/full_fig_p007_7.png]
Figure 8
Figure 8. Figure 8: PIC layout visualization from Apollo33 and LiDAR. 35 5. CONCLUSION AND FUTURE DIRECTION In this work, we present PoLaRIS, a comprehensive intelligent design automation framework to address the critical bottlenecks in large-scale PIC design. By unifying a fabrication-aw…

Discussion (0). Continue with ORCID to comment.

Reference graph

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