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LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines

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arxiv 2406.17132 v2 pith:ZQRR6WFT submitted 2024-06-24 cs.AR

Jitendra Bhandari , Johann Knechtel , Ramesh Narayanaswamy , Siddharth Garg , Ramesh Karri This is my paper · ORCID
classification cs.AR
keywords coveragedesignfeedbacktesttestbencheschipenhancegeneration
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This work investigates the potential of tailoring Large Language Models (LLMs), specifically GPT3.5 and GPT4, for the domain of chip testing. A key aspect of chip design is functional testing, which relies on testbenches to evaluate the functionality and coverage of Register-Transfer Level (RTL) designs. We aim to enhance testbench generation by incorporating feedback from commercial-grade Electronic Design Automation (EDA) tools into LLMs. Through iterative feedback from these tools, we refine the testbenches to achieve improved test coverage. Our case studies present promising results, demonstrating that this approach can effectively enhance test coverage. By integrating EDA tool feedback, the generated testbenches become more accurate in identifying potential issues in the RTL design. Furthermore, we extended our study to use this enhanced test coverage framework for detecting bugs in the RTL implementations

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Forward citations

Cited by 5 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generation

    cs.CR 2024-11 conditional novelty 6.0 of 10

    RTL-Breaker shows that fine-tuning an LLM on a small fraction of poisoned Verilog samples can make it generate malicious RTL code when a specific trigger appears, while still passing VerilogEval functional checks.

  2. Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI

    cs.AR 2024-11 conditional novelty 6.0 of 10

    Masala-CHAI automatically converts schematic images into SPICE netlists using object detection, line detection, and LLMs, producing a 7,500-example open dataset that boosts analog netlist generation Pass@1 by up to 46...

  3. CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design

    cs.SE 2024-11 conditional novelty 6.0 of 10

    A self-validating and self-correcting LLM framework raises testbench generation pass rate to 70.13%, up from 52.18% for the prior AutoBench framework.

  4. Hardware Design and Security in the Era of Chiplets and LLMs

    cs.CR 2026-08 accept novelty 2.0 of 10

    A survey uniting chiplet-hardware security and LLM-driven EDA security that identifies a missing bridge: LLM-based security tools are not yet tailored to 2.5D/3D chiplet systems.

  5. Legal Document Summarization: Enhancing Judicial Efficiency through Automation Detection

    cs.CL 2025-07 reject novelty 1.0 of 10

    A legal document summarization framework is described, but the experiments use four non-legal summarization datasets and generic equations, so the claimed judicial efficiency improvements are not established.

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