pith:3PC6X2FB
ADS-IMC: Accelerating Data Sorting with In-Memory Computation
In-memory sorting using 6T SRAM cuts data movement costs by keeping operations inside memory.
arxiv:2605.16213 v1 · 2026-05-15 · cs.AR
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\usepackage{pith}
\pithnumber{3PC6X2FBDFGHZNWN2ZY276Y7OT}
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Record completeness
Claims
This work represents the first exploration of in-memory sorting using 6T SRAM. The proposed architecture achieves a significant 3.4x reduction in latency compared to memristor-based IMC sorting.
That a functional 6T SRAM-based in-memory sorting circuit can be realized in hardware with the claimed latency benefit, without major area, power, or reliability penalties that would offset the gains.
Presents the first in-memory sorting design using 6T SRAM that delivers 3.4 times lower latency than memristor-based methods.
References
Receipt and verification
| First computed | 2026-05-20T00:01:58.305887Z |
|---|---|
| Builder | pith-number-builder-2026-05-17-v1 |
| Signature | Pith Ed25519
(pith-v1-2026-05) · public key |
| Schema | pith-number/v1.0 |
Canonical hash
dbc5ebe8a1194c7cb6cdd671affb1f74f36edf73626d1758553ab0d26497f3bf
Aliases
· · · · ·Agent API
Verify this Pith Number yourself
curl -sH 'Accept: application/ld+json' https://pith.science/pith/3PC6X2FBDFGHZNWN2ZY276Y7OT \
| jq -c '.canonical_record' \
| python3 -c "import sys,json,hashlib; b=json.dumps(json.loads(sys.stdin.read()), sort_keys=True, separators=(',',':'), ensure_ascii=False).encode(); print(hashlib.sha256(b).hexdigest())"
# expect: dbc5ebe8a1194c7cb6cdd671affb1f74f36edf73626d1758553ab0d26497f3bf
Canonical record JSON
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"license": "http://creativecommons.org/licenses/by/4.0/",
"primary_cat": "cs.AR",
"submitted_at": "2026-05-15T17:27:52Z",
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