pith:IGORLB57
FPGA-Accelerated Lock Management and Transaction Processing: Architecture, Optimization, and Design Space Exploration
Hardware lock agents on FPGA eliminate DRAM accesses to deliver up to 51 times the transaction throughput of CPU baselines in OLTP systems.
arxiv:2605.13398 v1 · 2026-05-13 · cs.AR · cs.DB · cs.DC
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\pithnumber{IGORLB57XQSRV7YOISOF7OAQET}
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Record completeness
Claims
The experiment results show up to 51X higher transaction throughput over the CPU baseline on the TPC-C benchmark.
That the FPGA design can sustain the reported throughput at scale without new bottlenecks in interconnect, memory hierarchy, or transaction coordination outside the lock agent.
FPGA lock agents with on-chip tables achieve up to 51X higher TPC-C throughput than CPU baselines by removing DRAM access overhead for lock operations.
References
Receipt and verification
| First computed | 2026-05-18T02:44:47.623276Z |
|---|---|
| Builder | pith-number-builder-2026-05-17-v1 |
| Signature | Pith Ed25519
(pith-v1-2026-05) · public key |
| Schema | pith-number/v1.0 |
Canonical hash
419d1587bfbc251aff0e449c5fb81024e369140c287470b24a5dab5908ffd431
Aliases
· · · · ·Agent API
Verify this Pith Number yourself
curl -sH 'Accept: application/ld+json' https://pith.science/pith/IGORLB57XQSRV7YOISOF7OAQET \
| jq -c '.canonical_record' \
| python3 -c "import sys,json,hashlib; b=json.dumps(json.loads(sys.stdin.read()), sort_keys=True, separators=(',',':'), ensure_ascii=False).encode(); print(hashlib.sha256(b).hexdigest())"
# expect: 419d1587bfbc251aff0e449c5fb81024e369140c287470b24a5dab5908ffd431
Canonical record JSON
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