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pith:ILNMSBVX

pith:2026:ILNMSBVXPVEKT3ZOCSHAOF2O4N
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ITHICA: Intra-Thread Instruction Checking Approach for Defect-Induced Silent Data Corruptions

Caroline Trippel, Eric X. Liu, Ioanna Vavelidou, Mike Fuller, Subhasish Mitra, Subho S. Banerjee

Intra-thread instruction duplication detects 39% more defective servers by catching inconsistent defect errors.

arxiv:2605.15638 v1 · 2026-05-15 · cs.AR · cs.SE

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3 Author claim open · sign in to claim
4 Citations open
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Claims

C1strongest claim

ITHICA error checks detect 39% more defective servers than native checks within the ITHICA tests derived from our baseline programs, and enable novel findings on defect behavior that challenge conclusions drawn by prior hyperscaler fleet studies.

C2weakest assumption

The assumption that the most pernicious defects cause inconsistent errors such that two executions of the same instruction within the same thread, given the same inputs, can produce different architectural outputs depending on the execution context.

C3one line summary

ITHICA generates functional tests via intra-thread instruction duplication and comparison, detecting 39% more defective servers than baseline methods on over 3000 real CPUs while revealing new defect behaviors.

References

88 extracted · 88 resolved · 1 Pith anchors

[1] LIBRA: Enabling Workload-Aware Multi-Dimensional Network Topology Optimization for Distributed Training of Large AI Models 2024 · doi:10.1109/ispass61541.2024.00046
[2] Andreas Abel and Jan Reineke. 2019. uops.info: Characterizing Latency, Through- put, and Port Usage of Instructions on Intel Microarchitectures. InASPLOS (Providence, RI, USA)(ASPLOS ’19). ACM, New Yo 2019 · doi:10.1145/3297858.3304062
[3] abseil 2024. Abseil. https://github.com/abseil/abseil-cpp 2024
[4] Paul, Ming Zhang, and Subhasish Mitra 2007 · doi:10.1109/vts.2007.22
[5] Chang, Chao-Wen Tseng, Chien-Mo James Li, Mike Purtell, and Edward Joseph McCluskey 1998

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Receipt and verification
First computed 2026-05-20T00:01:09.496264Z
Builder pith-number-builder-2026-05-17-v1
Signature Pith Ed25519 (pith-v1-2026-05) · public key
Schema pith-number/v1.0

Canonical hash

42dac906b77d48a9ef2e148e07174ee359dd6f9477d5952e45fcfc2d0c6fe3bd

Aliases

arxiv: 2605.15638 · arxiv_version: 2605.15638v1 · doi: 10.48550/arxiv.2605.15638 · pith_short_12: ILNMSBVXPVEK · pith_short_16: ILNMSBVXPVEKT3ZO · pith_short_8: ILNMSBVX
Agent API
Verify this Pith Number yourself
curl -sH 'Accept: application/ld+json' https://pith.science/pith/ILNMSBVXPVEKT3ZOCSHAOF2O4N \
  | jq -c '.canonical_record' \
  | python3 -c "import sys,json,hashlib; b=json.dumps(json.loads(sys.stdin.read()), sort_keys=True, separators=(',',':'), ensure_ascii=False).encode(); print(hashlib.sha256(b).hexdigest())"
# expect: 42dac906b77d48a9ef2e148e07174ee359dd6f9477d5952e45fcfc2d0c6fe3bd
Canonical record JSON
{
  "metadata": {
    "abstract_canon_sha256": "2aab2bbf3611f7ab31490599e52bf327e080fee9ffe1d0cea717169e76cebbf8",
    "cross_cats_sorted": [
      "cs.SE"
    ],
    "license": "http://arxiv.org/licenses/nonexclusive-distrib/1.0/",
    "primary_cat": "cs.AR",
    "submitted_at": "2026-05-15T05:43:33Z",
    "title_canon_sha256": "5bb8486269fc0e2ceb4cbccd6543c387fc4f0af93adc98cbcebd49b7509e3cc2"
  },
  "schema_version": "1.0",
  "source": {
    "id": "2605.15638",
    "kind": "arxiv",
    "version": 1
  }
}