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Abhishek Jain

Identifiers

  • name variant Abhishek Jain 0.60 · backfill

Papers (4)

  1. An Area-Efficient FPGA Overlay using DSP Block based Time-multiplexed Functional Units cs.AR · 2016 · author #2
  2. Early Development of UVM based Verification Environment of Image Signal Processing Designs using TLM Reference Model of RTL cs.SE · 2014 · author #1
  3. Accelerating SystemVerilog UVM Based VIP to Improve Methodology for Verification of Image Signal Processing Designs Using HW Emulator cs.OH · 2014 · author #1
  4. Generic System Verilog Universal Verification Methodology based Reusable Verification Environment for Efficient Verification of Image Signal Processing IPs/SoCs cs.OH · 2013 · author #1

Mentions

  • 1408.1150 #1 · backfill · confidence 0.70 Abhishek Jain
  • 1401.3554 #1 · backfill · confidence 0.70 Abhishek Jain
  • 1301.2858 #1 · backfill · confidence 0.70 Abhishek Jain

Frequent Coauthors