Abhishek Jain
Identifiers
- name variant Abhishek Jain 0.60 · backfill
Papers (4)
- An Area-Efficient FPGA Overlay using DSP Block based Time-multiplexed Functional Units cs.AR · 2016 · author #2
- Early Development of UVM based Verification Environment of Image Signal Processing Designs using TLM Reference Model of RTL cs.SE · 2014 · author #1
- Accelerating SystemVerilog UVM Based VIP to Improve Methodology for Verification of Image Signal Processing Designs Using HW Emulator cs.OH · 2014 · author #1
- Generic System Verilog Universal Verification Methodology based Reusable Verification Environment for Efficient Verification of Image Signal Processing IPs/SoCs cs.OH · 2013 · author #1
Mentions
Frequent Coauthors
- Dr. Hima Gupta 2 shared papers
- Ajay Goyal 1 shared papers
- Douglas Maskell 1 shared papers
- Giuseppe Bonanno 1 shared papers
- Hima Gupta 1 shared papers
- Krishna Kumar 1 shared papers
- Piyush Kumar Gupta 1 shared papers
- Sachish Dhar 1 shared papers
- Sandeep Jana 1 shared papers
- Suhaib A. Fahmy 1 shared papers
- Xiangwei Li 1 shared papers