Thomas Dalgaty

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Papers (1)

1. Hardware-Accelerated Event-Graph Neural Networks for Low-Latency Time-Series Classification on SoC FPGA cs.LG · 2025 · author #9

Mentions

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Frequent Coauthors

• Hiroaki Nishi 1 shared papers
• Hiroshi Nakano 1 shared papers
• Kamil Jeziorek 1 shared papers
• Krzysztof Blachut 1 shared papers
• Manon Dampfhoffer 1 shared papers
• Piotr Wzorek 1 shared papers
• Thomas Mesquida 1 shared papers
• Tomasz Kryjak 1 shared papers