pith. sign in

arxiv: 2503.06629 · v1 · submitted 2025-03-09 · 💻 cs.LG · cs.AI· eess.SP

Hardware-Accelerated Event-Graph Neural Networks for Low-Latency Time-Series Classification on SoC FPGA

Hiroshi Nakano , Krzysztof Blachut , Kamil Jeziorek , Piotr Wzorek , Manon Dampfhoffer , Thomas Mesquida , Hiroaki Nishi , Tomasz Kryjak
show 1 more author
Thomas Dalgaty
This is my paper

Pith reviewed 2026-05-23 00:28 UTC · model grok-4.3

classification 💻 cs.LG cs.AIeess.SP
keywords event-graph neural networkstime-series classificationSoC FPGASHD datasetartificial cochleaspiking neural networkslow-latency inference
0
0 comments X

The pith

An event-graph neural network on SoC FPGA classifies time-series at 92.7 percent accuracy using sparse events from an artificial cochlea model.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper shows that converting time-series signals into sparse event data via an artificial cochlea model lets an event-graph neural network run efficiently on FPGA hardware. This reduces the calculations needed for classification compared to other AI methods. A reader would care because it enables real-time low-power predictions on edge devices handling growing sensor data. The design reaches 92.7 percent accuracy on the SHD dataset while using fewer parameters than state-of-the-art models and lower resources than prior FPGA spiking networks.

Core claim

The authors present a hardware implementation of an event-graph neural network for time-series classification on a SoC FPGA. They use an artificial cochlea model to convert input signals into sparse event data which reduces calculations. On the SHD dataset the base model achieves 92.7 percent accuracy only 2.4 percent below one state-of-the-art model while using over 10 percent fewer parameters. The quantized model reaches 92.3 percent accuracy outperforming FPGA spiking networks by up to 19.3 percent with lower resource use and latency.

What carries the argument

Event-graph neural network operating on sparse event data generated by an artificial cochlea model and accelerated on SoC FPGA hardware.

If this is right

  • The base model reaches 92.7 percent accuracy on SHD while using over 10 percent fewer parameters than one state-of-the-art competitor.
  • The quantized model achieves 92.3 percent accuracy and surpasses two FPGA spiking networks by 19.3 percent and 4.5 percent.
  • The hardware design reduces computational resources and latency relative to the compared spiking networks.
  • Sparse event representation from the cochlea model cuts the number of calculations required for each classification.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The cochlea-plus-event-graph pipeline could be tested on vibration or biomedical signals to check whether the accuracy advantage holds.
  • Direct power measurements on identical hardware would clarify practical energy savings over dense networks.

Load-bearing premise

The artificial cochlea model converts input time-series signals into a sparse event-data format that preserves sufficient information for the event-graph neural network to achieve high classification accuracy without major information loss.

What would settle it

Running the same pipeline on a non-audio time-series dataset and comparing accuracy plus measured FPGA latency against a dense neural network baseline.

Figures

Figures reproduced from arXiv: 2503.06629 by Hiroaki Nishi, Hiroshi Nakano, Kamil Jeziorek, Krzysztof Blachut, Manon Dampfhoffer, Piotr Wzorek, Thomas Dalgaty, Thomas Mesquida, Tomasz Kryjak.

Figure 1
Figure 1. Figure 1: Overview of our hardware-accelerated event-graph neural network imple [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Spectro-Temporal Spike Rasters from the SHD dataset. [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Overview of the graph generation and convolution modules. The [PITH_FULL_IMAGE:figures/full_fig_p007_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Model complexity analysis in term of FLOPs. The figures illustrate not [PITH_FULL_IMAGE:figures/full_fig_p012_4.png] view at source ↗
read the original abstract

As the quantities of data recorded by embedded edge sensors grow, so too does the need for intelligent local processing. Such data often comes in the form of time-series signals, based on which real-time predictions can be made locally using an AI model. However, a hardware-software approach capable of making low-latency predictions with low power consumption is required. In this paper, we present a hardware implementation of an event-graph neural network for time-series classification. We leverage an artificial cochlea model to convert the input time-series signals into a sparse event-data format that allows the event-graph to drastically reduce the number of calculations relative to other AI methods. We implemented the design on a SoC FPGA and applied it to the real-time processing of the Spiking Heidelberg Digits (SHD) dataset to benchmark our approach against competitive solutions. Our method achieves a floating-point accuracy of 92.7% on the SHD dataset for the base model, which is only 2.4% and 2% less than the state-of-the-art models with over 10% and 67% fewer model parameters, respectively. It also outperforms FPGA-based spiking neural network implementations by 19.3% and 4.5%, achieving 92.3% accuracy for the quantised model while using fewer computational resources and reducing latency.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 0 minor

Summary. The paper presents a hardware implementation of an event-graph neural network on a SoC FPGA for low-latency time-series classification. It converts input signals to sparse events via an artificial cochlea model, benchmarks on the SHD dataset, and reports 92.7% floating-point accuracy (base model) and 92.3% for the quantized model, claiming these are competitive with SOTA while using over 10% and 67% fewer parameters, plus lower latency and resources than FPGA SNN baselines.

Significance. If the accuracy claims hold under matched preprocessing and the hardware metrics are reproducible, the work provides a concrete demonstration of event-based graph networks achieving competitive accuracy with reduced parameters on FPGA hardware. This could support low-power edge deployment for time-series tasks, with the reported parameter reductions and latency benefits as potentially useful contributions if the experimental controls are strengthened.

major comments (2)
  1. [Abstract] Abstract: The central accuracy claims (92.7% base, 92.3% quantized) and the attribution of the 2.4%/2% gaps to the event-graph architecture rest on comparisons to SOTA models, but no verification is supplied that the artificial cochlea conversion (filter banks, spike encoding, sparsity) matches the preprocessing used in the referenced works; any mismatch would mean the performance delta is not load-bearing evidence for the proposed method.
  2. [Abstract] Abstract: The reported accuracies and outperformance margins (19.3% and 4.5% over FPGA SNNs) are stated without error bars, dataset splits, training protocol, or hardware resource tables, preventing assessment of whether the central performance and efficiency claims are statistically supported or reproducible.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the detailed and constructive comments. We address each major point below and have prepared revisions to strengthen the presentation of our results.

read point-by-point responses

  1. Referee: [Abstract] Abstract: The central accuracy claims (92.7% base, 92.3% quantized) and the attribution of the 2.4%/2% gaps to the event-graph architecture rest on comparisons to SOTA models, but no verification is supplied that the artificial cochlea conversion (filter banks, spike encoding, sparsity) matches the preprocessing used in the referenced works; any mismatch would mean the performance delta is not load-bearing evidence for the proposed method.

    Authors: The full manuscript (Section 3) specifies the artificial cochlea parameters (filter banks, spike encoding thresholds, and sparsity levels) taken directly from the original SHD reference and the SOTA graph-based works cited. This ensures the preprocessing pipeline is identical. To make the match explicit for readers of the abstract, we will revise the abstract to include a short clause confirming the use of the standard SHD preprocessing pipeline. This directly addresses the concern without altering the reported numbers. revision: yes

  2. Referee: [Abstract] Abstract: The reported accuracies and outperformance margins (19.3% and 4.5% over FPGA SNNs) are stated without error bars, dataset splits, training protocol, or hardware resource tables, preventing assessment of whether the central performance and efficiency claims are statistically supported or reproducible.

    Authors: The manuscript body already details the training protocol, standard SHD train/test splits, and hardware resource utilization (LUTs, DSPs, latency) in Sections 4 and 5. We agree the abstract would benefit from additional statistical context. In revision we will (i) report mean accuracy and standard deviation over five independent training runs and (ii) add a compact hardware resource table (or reference to Table 3) so the efficiency claims can be evaluated directly from the abstract. These additions improve reproducibility without changing the core results. revision: yes

Circularity Check

0 steps flagged

No circularity: empirical hardware results on external benchmark

full rationale

The paper describes an FPGA implementation of an event-graph neural network for SHD time-series classification after cochlea-based event conversion. Reported accuracies (92.7% base, 92.3% quantized) are direct hardware measurements compared to external SOTA references. No equations, parameter fits, predictions, or self-citations are presented that reduce any claim to its own inputs by construction. The cochlea preprocessing step is an engineering choice whose information preservation is an empirical assumption, not a definitional loop. This is a standard self-contained implementation paper.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

Abstract-only review prevents identification of specific free parameters or axioms; no invented entities are mentioned.

pith-pipeline@v0.9.0 · 5813 in / 1030 out tokens · 62222 ms · 2026-05-23T00:28:49.618300+00:00 · methodology

discussion (0)

Sign in with ORCID, Apple, or X to comment. Anyone can read and Pith papers without signing in.

Lean theorems connected to this paper

Citations machine-checked in the Pith Canon. Every link opens the source theorem in the public Lean library.

What do these tags mean?
matches
The paper's claim is directly supported by a theorem in the formal canon.
supports
The theorem supports part of the paper's argument, but the paper may add assumptions or extra steps.
extends
The paper goes beyond the formal theorem; the theorem is a base layer rather than the whole result.
uses
The paper appears to rely on the theorem as machinery.
contradicts
The paper's claim conflicts with a theorem or certificate in the canon.
unclear
Pith found a possible connection, but the passage is too broad, indirect, or ambiguous to say the theorem truly supports the claim.

Reference graph

Works this paper leans on

38 extracted references · 38 canonical work pages · 1 internal anchor

  1. [1]

    IEEE Transactions on Neural Networks and Learning Systems (2023).https://doi.org/10.1109/TNNLS.2023.3291371

    Ren, L., Jia, Z., Laili, Y., Huang, D.: Deep learning for time-series prediction in IIoT: progress, challenges, and prospects. IEEE Transactions on Neural Networks and Learning Systems (2023).https://doi.org/10.1109/TNNLS.2023.3291371

    work page doi:10.1109/tnnls.2023.3291371 2023

  2. [2]

    Philo- sophical Transactions of the Royal Society A379(2194), 20200209 (2021).https: //doi.org/10.1098/rsta.2020.0209

    Lim, B., Zohren, S.: Time-series forecasting with deep learning: a survey. Philo- sophical Transactions of the Royal Society A379(2194), 20200209 (2021).https: //doi.org/10.1098/rsta.2020.0209

    work page doi:10.1098/rsta.2020.0209 2021

  3. [3]

    IEEE Transactions on Indus- trial Informatics16(10), 6263–6271 (2020).https://doi.org/10.1109/TII.2020

    Saufi, S.R., Ahmad, Z.A.B., Leong, M.S., Lim, M.H.: Gearbox fault diagnosis us- ing a deep learning model with limited data sample. IEEE Transactions on Indus- trial Informatics16(10), 6263–6271 (2020).https://doi.org/10.1109/TII.2020. 2967822

    work page doi:10.1109/tii.2020 2020

  4. [4]

    New England Journal of Medicine 349(19), 1836–1847 (2003).https://doi.org/10.1056/NEJMra035432

    DiMarco, J.P.: Implantable cardioverter–defibrillators. New England Journal of Medicine 349(19), 1836–1847 (2003).https://doi.org/10.1056/NEJMra035432

    work page doi:10.1056/nejmra035432 2003

  5. [5]

    In: 2024 IEEE Nordic Circuits and Systems Conference (NorCAS)

    Al-Ameri, Y., Nguyen, M., Westerlund, T.: Fpga-based hardware acceleration for deep learning in mobile robotics. In: 2024 IEEE Nordic Circuits and Systems Conference (NorCAS). pp. 1–7 (2024).https://doi.org/10.1109/NorCAS64408. 2024.10752450

    work page doi:10.1109/norcas64408 2024

  6. [6]

    In: 2020 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)

    Al-Ali, F., Gamage, T.D., Nanayakkara, H.W., Mehdipour, F., Ray, S.K.: Novel casestudy and benchmarking of alexnet for edge ai: From cpu and gpu to fpga. In: 2020 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE). pp. 1–4 (2020).https://doi.org/10.1109/CCECE47787.2020.9255739

    work page doi:10.1109/ccece47787.2020.9255739 2020

  7. [7]

    ACM Trans

    Guo, K., Zeng, S., Yu, J., Wang, Y., Yang, H.: [dl] a survey of fpga-based neural network inference accelerators. ACM Trans. Reconfigurable Technol. Syst.12(1) (Mar 2019). https://doi.org/10.1145/3289185

    work page doi:10.1145/3289185 2019

  8. [8]

    IEEE Transactions on Pattern Analysis and Machine Intelligence 44(1), 154–180 (2020).https://doi.org/10.1109/TPAMI.2020.3008413

    Gallego, G., Delbrück, T., Orchard, G., Bartolozzi, C., Taba, B., Censi, A., Leutenegger, S., Davison, A.J., Conradt, J., Daniilidis, K., et al.: Event-based vision: A survey. IEEE Transactions on Pattern Analysis and Machine Intelligence 44(1), 154–180 (2020).https://doi.org/10.1109/TPAMI.2020.3008413

    work page doi:10.1109/tpami.2020.3008413 2020

  9. [9]

    IEEE Transactions on Biomedical Circuits and Systems8(4), 453–464 (2013).https://doi.org/10

    Liu, S.C., van Schaik, A., Minch, B.A., Delbruck, T.: Asynchronous Binaural Spatial Audition Sensor With 2 ×64×4 Channel Output. IEEE Transactions on Biomedical Circuits and Systems8(4), 453–464 (2013).https://doi.org/10. 1109/TBCAS.2013.2281834

    work page arXiv 2013

  10. [10]

    In: 2024 IEEE International Solid-State Circuits Conference (ISSCC)

    Mostafa, A., Hardy, E., Badets, F.: 17.8 0.4 v 988nw time-domain audio feature extraction for keyword spotting using injection-locked oscillators. In: 2024 IEEE International Solid-State Circuits Conference (ISSCC). vol. 67, pp. 328–330. IEEE (2024). https://doi.org/10.1109/ISSCC49657.2024.10454389

    work page doi:10.1109/isscc49657.2024.10454389 2024

  11. [11]

    In: 2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS)

    Ortner, T., Pes, L., Gentinetta, J., Frenkel, C., Pantazi, A.: Online spatio-temporal learning with target projection. In: 2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS). pp. 1–5. IEEE (2023).https: //doi.org/10.1109/AICAS57966.2023.10168623

    work page doi:10.1109/aicas57966.2023.10168623 2023

  12. [12]

    IEEE Transactions on Emerging Topics in Computing (01), 1–15 (Dec 2024)

    Carpegna, A., Savino, A., Carlo, S.D.: Spiker+: a framework for the generation of efficient Spiking Neural Networks FPGA accelerators for inference at the edge. IEEE Transactions on Emerging Topics in Computing (01), 1–15 (Dec 2024). https://doi.org/10.1109/TETC.2024.3511676

    work page doi:10.1109/tetc.2024.3511676 2024

  13. [13]

    Nature Communications15(1), 142 (2024)

    Dalgaty, T., Moro, F., Demirağ, Y., De Pra, A., Indiveri, G., Vianello, E., Payvand, M.: Mosaic: in-memory computing and routing for small-world spike- based neuromorphic systems. Nature Communications15(1), 142 (2024). https: //doi.org/10.1038/s41467-023-44365-x Hardware-Accelerated Event-Graph Neural Networks 17

    work page doi:10.1038/s41467-023-44365-x 2024

  14. [14]

    IEEE Trans- actions on Emerging Topics in Computational Intelligence7(3), 731–741 (2023)

    Dampfhoffer, M., Mesquida, T., Valentian, A., Anghel, L.: Are SNNs Really More Energy-Efficient Than ANNs? an In-Depth Hardware-Aware Study. IEEE Trans- actions on Emerging Topics in Computational Intelligence7(3), 731–741 (2023). https://doi.org/10.1109/TETCI.2022.3214509

    work page doi:10.1109/tetci.2022.3214509 2023

  15. [15]

    SNN Event-camera Dichotomy and Perspectives For Event-Graph Neural Networks

    Dalgaty, T., Mesquida, T., Joubert, D., Sironi, A., Soubeyrat, C., Vivet, P., Posch, C.: The CNN vs. SNN Event-camera Dichotomy and Perspectives For Event-Graph Neural Networks. In: 2023 Design, Automation & Test in Europe Conference & Ex- hibition (DATE). pp. 1–6. IEEE (2023).https://doi.org/10.23919/DATE56975. 2023.10137023

    work page doi:10.23919/date56975 2023

  16. [16]

    Walk in the cloud: Learning curves for point clouds shape analysis, pp

    Li, Y., Zhou, H., Yang, B., Zhang, Y., Cui, Z., Bao, H., Zhang, G.: Graph-based asynchronous event processing for rapid object recognition. In: Proceedings of the IEEE/CVF International Conference on Computer Vision. pp. 934–943 (2021). https://doi.org/10.1109/ICCV48922.2021.00097

    work page doi:10.1109/iccv48922.2021.00097 2021

  17. [17]

    In: Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR) Workshops

    Dalgaty, T., Mesquida, T., Joubert, D., Sironi, A., Vivet, P., Posch, C.: Hugnet: Hemi-spherical update graph neural network applied to low-latency event-based optical flow. In: Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR) Workshops. pp. 3952–3961 (June 2023).https: //doi.org/10.1109/CVPRW59228.2023.00411

    work page doi:10.1109/cvprw59228.2023.00411 2023

  18. [18]

    In: https://proceedings.bmvc2023.org/

    Mesquida, T., Dampfhoffer, M., Dalgaty, T., Vivet, P., Sironi, A., Posch, C.: G2N2: Lightweight event stream classification with GRU graph neural networks. In: https://proceedings.bmvc2023.org/. p. 660. https://proceedings.bmvc2023.org/, Aberdeen, United Kingdom (Nov 2023), https://cea.hal.science/cea-04321175

    work page 2023

  19. [19]

    In: 2023 Signal Processing: Algorithms, Architectures, Arrangements, and Applications (SPA)

    Jeziorek, K., Pinna, A., Kryjak, T.: Memory-efficient graph convolutional net- works for object classification and detection with event cameras. In: 2023 Signal Processing: Algorithms, Architectures, Arrangements, and Applications (SPA). pp. 160–165. IEEE (2023).https://doi.org/10.23919/SPA59660.2023.10274464

    work page doi:10.23919/spa59660.2023.10274464 2023

  20. [20]

    Rafeldt, L., Mesquida, T., Nakano, H., Dampfhoffer, M., Moro, F., Vivet, P., Pay- vand, M., Dalgaty, T.: Event-based audio prediction with spectro-temporal event- graphs (2025)

    work page 2025

  21. [21]

    Jeziorek, K., Wzorek, P., Blachut, K., Pinna, A., Kryjak, T.: Embedded Graph Convolutional Networks for Real-Time Event Data Processing on SoC FPGAs (2024), https://arxiv.org/abs/2406.07318

    work page arXiv 2024

  22. [22]

    arXiv preprint arXiv:2404.19489 (2024).https://doi

    Yang, Y., Kneip, A., Frenkel, C.: Evgnn: An event-driven graph neural network accelerator for edge vision. arXiv preprint arXiv:2404.19489 (2024).https://doi. org/10.48550/arXiv.2404.19489

    work page doi:10.48550/arxiv.2404.19489 2024

  23. [23]

    IEEE Transactions on Neural Networks and Learning Systems33(7), 2744–2757 (2022).https://doi

    Cramer, B., Stradmann, Y., Schemmel, J., Zenke, F.: The heidelberg spiking data sets for the systematic evaluation of spiking neural networks. IEEE Transactions on Neural Networks and Learning Systems33(7), 2744–2757 (2022).https://doi. org/10.1109/TNNLS.2020.3044364

    work page doi:10.1109/tnnls.2020.3044364 2022

  24. [24]

    Frontiers in Neuroscience 16 (2022)

    Bittar, A., Garner, P.N.: A surrogate gradient spiking baseline for speech com- mand recognition. Frontiers in Neuroscience 16 (2022). https://doi.org/10. 3389/fnins.2022.865897

    work page arXiv 2022

  25. [25]

    In: Pimenidis, E., Angelov, P., Jayne, C., Papaleonidas, A., Aydin, M

    Dampfhoffer, M., Mesquida, T., Valentian, A., Anghel, L.: Investigating current- based and gating approaches for accurate and energy-efficient spiking recurrent neural networks. In: Pimenidis, E., Angelov, P., Jayne, C., Papaleonidas, A., Aydin, M. (eds.) Artificial Neural Networks and Machine Learning – ICANN 2022. pp. 359–370. Springer Nature Switzerlan...

    work page 2022

  26. [26]

    Neuromorphic Computing and Engineering2(4), 044016 (Dec 2022)

    Rossbroich, J., Gygax, J., Zenke, F.: Fluctuation-driven initialization for spiking neural network training. Neuromorphic Computing and Engineering2(4), 044016 (Dec 2022). https://doi.org/10.1088/2634-4386/ac97bb

    work page doi:10.1088/2634-4386/ac97bb 2022

  27. [27]

    Nature Communications15(3446) (2024), https://doi.org/10.1038/s41467-024-47764-w

    D’Agostino, S., Moro, F., Torchet, T., Demirag, Y., Grenouillet, L., Indiveri, G., Vianello,E.,Payvand,M.:Denram:Neuromorphicdendriticarchitecturewithrram for efficient temporal processing with delays. Nature Communications15(3446) (2024), https://doi.org/10.1038/s41467-024-47764-w

    work page doi:10.1038/s41467-024-47764-w 2024

  28. [28]

    Hammouamri, I., Khalfaoui-Hassani, I., Masquelier, T.: Learning delays in spiking neural networks using dilated convolutions with learnable spacings (2023),https: //arxiv.org/abs/2306.17670

    work page arXiv 2023

  29. [29]

    Malettira, P.G., Negi, S., Ponghiran, W., Roy, K.: TSkips: Efficiency Through Explicit Temporal Delay Connections in Spiking Neural Networks (2024),https: //arxiv.org/abs/2411.16711

    work page arXiv 2024

  30. [30]

    Frontiers in Neuroscience17 (2023)

    Sun, P., Chua, Y., Devos, P., Botteldooren, D.: Learnable axonal delay in spiking neural networks improves spoken word recognition. Frontiers in Neuroscience17 (2023). https://doi.org/10.3389/fnins.2023.1275944

    work page doi:10.3389/fnins.2023.1275944 2023

  31. [31]

    Frontiers in Neuroscience16 (2022)

    Yu, C., Gu, Z., Li, D., Wang, G., Wang, A., Li, E.: Stsc-snn: Spatio-temporal synaptic connection with temporal convolution and attention for spiking neural networks. Frontiers in Neuroscience16 (2022). https://doi.org/10.3389/fnins. 2022.1079357

    work page doi:10.3389/fnins 2022

  32. [32]

    Matinizadeh, S., Pacik-Nelson, N., Polykretis, I., Tishbi, K., Kumar, S., Varshika, M.L., Mohammadhassani, A., Mishra, A., Kandasamy, N., Shackleford, J., Gallo, E., Das, A.: A fully-configurable open-source software-defined digital quantized spiking neural core architecture (2024),https://arxiv.org/abs/2404.02248

    work page arXiv 2024

  33. [33]

    In: 2022 IEEE Custom Integrated Circuits Conference (CICC)

    Basu, A., Deng, L., Frenkel, C., Zhang, X.: Spiking neural network integrated circuits: A review of trends and future directions. In: 2022 IEEE Custom Integrated Circuits Conference (CICC). pp. 1–8. IEEE (2022).https://doi.org/10.1109/ CICC53496.2022.9772783

    work page arXiv 2022

  34. [34]

    In: 2024 27th Euromicro Con- ference on Digital System Design (DSD)

    Kryjak, T.: Event-based vision on fpgas-a survey. In: 2024 27th Euromicro Con- ference on Digital System Design (DSD). pp. 541–550. IEEE (2024). https: //doi.org/10.1109/DSD64264.2024.00078

    work page doi:10.1109/dsd64264.2024.00078 2024

  35. [35]

    Fron- tiers in Neuroscience17, 1125210 (2023).https://doi.org/10.3389/fnins.2023

    Xu, Y., Perera, S., Bethi, Y., Afshar, S., van Schaik, A.: Event-driven spectrotem- poral feature extraction and classification using a silicon cochlea model. Fron- tiers in Neuroscience17, 1125210 (2023).https://doi.org/10.3389/fnins.2023. 1125210

    work page doi:10.3389/fnins.2023 2023

  36. [36]

    In: 2017 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

    Charles, R.Q., Su, H., Kaichun, M., Guibas, L.J.: Pointnet: Deep learning on point sets for 3d classification and segmentation. In: 2017 IEEE Conference on Computer Vision and Pattern Recognition (CVPR). pp. 77–85 (2017).https://doi.org/10. 1109/CVPR.2017.16

    work page 2017

  37. [37]

    In: Proceedings of the IEEE conference on computer vi- sion and pattern recognition

    Jacob, B., Kligys, S., Chen, B., Zhu, M., Tang, M., Howard, A., Adam, H., Kalenichenko,D.:Quantizationandtrainingofneuralnetworksforefficientinteger- arithmetic-only inference. In: Proceedings of the IEEE conference on computer vi- sion and pattern recognition. pp. 2704–2713 (2018).https://doi.org/10.1109/ CVPR.2018.00286

    work page arXiv 2018

  38. [38]

    Fast Graph Representation Learning with PyTorch Geometric

    Fey, M., Lenssen, J.E.: Fast graph representation learning with pytorch geometric. ArXiv abs/1903.02428 (2019), https://api.semanticscholar.org/CorpusID: 70349949

    work page internal anchor Pith review Pith/arXiv arXiv 1903