The authors integrate a parameterized posit FPU into a SHAKTI RISC-V core, claim the first posit-enabled RISC-V processor, and report accuracy benefits over IEEE-754 in selected applications.
Be more familiar with our enemies and pave the way forward: A review of the roles bugs played in software failures,
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PERI: A Posit Enabled RISC-V Core
The authors integrate a parameterized posit FPU into a SHAKTI RISC-V core, claim the first posit-enabled RISC-V processor, and report accuracy benefits over IEEE-754 in selected applications.