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REVIEW 5 major objections 7 minor 32 references

PERI: A Posit Enabled RISC-V Core

T0 review · 5 major / 7 minor · reviewed 2026-08-14 · deepseek-v4-flash

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Pith's one-line read The paper claims the first complete RISC-V core with a feature-complete, parameterized posit FPU that can switch exponent sizes at run time, and reports it working on an FPGA at 100 MHz.

desk verdict A full posit FPU in an open RISC-V core is a real first, but the runtime es-switch path is untested and the RTL is private—treat the headline as plausible, not verified. read the letter →

arxiv 1908.01466 v1 pith:URL5D62W submitted 2019-08-05 cs.AR

Sugandha Tiwari , Neel Gala , Chester Rebeiro , V. Kamakoti This is my paper · ORCID
classification cs.AR
keywords positarithmeticRISC-Vfloating-pointunitIEEE754FPGAimplementationdynamicexponentsizeRoCCacceleratorcustomISAextension
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper proposes putting posit arithmetic, an alternative to IEEE 754 floating point, into a real RISC-V processor rather than leaving it as standalone arithmetic blocks. It claims PERI is the first complete RISC-V core with a feature-complete posit floating-point unit, integrated either as a normal execution unit or as an accelerator through the RoCC coprocessor interface. The unit is parameterized, and for 32-bit posits it can switch at run time between exponent sizes es=2 and es=3 so software can trade precision against dynamic range. Synthesis on an Artix-7 FPGA reports 3,507 slice LUTs, 1,294 slice registers, and a 100 MHz clock, and several small applications show accuracy or range benefits over IEEE 754 at the same bit width.

What carries the argument

The load-bearing object is the parameterized posit FPU, built from a common posit decoder and encoder, a fused multiply-add block reused for add, subtract, and multiply, iterative non-restoring divider and square-root units, integer-to-posit and posit-to-integer converters, comparisons done with integer logic, sign injection, classify, plus an es-mode field in the posit control and status register and an FCVT.ES instruction for switching exponent sizes. The decoder/encoder pair is what makes switching cheap: a number is decoded under the source es and encoded under the target es, with only a few extra shifts needed to handle es=2 alongside es=3.

What would settle it

Implement the seven published algorithms in bit-accurate software or RTL, run random and corner-case inputs through every operation at es=3 and through FCVT.ES switching, and compare outputs with the software posit reference the paper used; a single mismatch in the es=3 or switching path would break the claim.

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Extended reading notes

Core claim

The central claim is that a complete, parameterized posit FPU can be bolted onto the RISC-V 'F' extension with minimal change: the same instruction encodings and register file work if the control and status register carries an es-mode field, and the custom opcode space can host a wider posit coprocessor. The paper reports that both integration routes—tightly coupled execution unit and RoCC accelerator—work with the baseline in-order RISC-V core, that the FPU covers all F-extension operations in posit form, and that adding a second exponent size costs about 15% more LUTs and 8% more registers, enabling run-time switching through an FCVT.ES instruction that re-encodes a posit from one es value to another.

Load-bearing premise

The claim that PERI is the first complete posit-enabled RISC-V core rests on the untested assumption that the unpublished RTL correctly implements the es=3 and dynamic-switching paths, since the random verification reported in the paper covers es=2 only.

Editorial extensions

If this is right

  • A RISC-V core that already speaks RoCC can gain posit arithmetic without touching its pipeline, and IEEE-754 and posit units can coexist on the same chip.
  • Run-time switching between es=2 and es=3 lets one implementation cover high-precision and high-dynamic-range workloads, with software choosing the mode during computation.
  • The reported application results—lower mean percentage error in sine, cosine, exponential, and FFT calculations, and clustering that survives inputs where IEEE-754 overflows—suggest that 32-bit posit can carry more useful information than 32-bit IEEE-754.
  • The proposed instruction mappings and the FCVT.ES format give the RISC-V ecosystem a concrete starting point for compiler support, which the paper identifies as the missing piece.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The most direct check that would settle the main claim is exhaustive bit-level comparison of every operation at es=3 and of FCVT.ES switching against a software posit reference, since the paper's reported random tests do not cover those paths.
  • If runtime es switching proves correct, the same decode-then-encode trick generalizes to other parameterized number formats controlled by a CSR mode field, suggesting a template for future arithmetic units.
  • The memcpy-and-hex-constant toolchain workaround will not scale; the real-world significance of PERI depends on compiler support and on a standard calling convention for posit data following.
  • The accuracy comparisons are on small kernels, so a stronger test would be an end-to-end application such as machine-learning inference or scientific simulation, where rounding errors accumulate over many operations.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

5 major / 7 minor

Summary. The paper proposes PERI, a posit-enabled RISC-V core built by integrating a parameterized Bluespec SystemVerilog posit FPU into the SHAKTI C-class core. The FPU implements the RV32F instruction set in posit form, supports dynamic switching between es=2 and es=3 at runtime via a new FCVT.ES instruction, and can be integrated either as a tightly coupled execution unit or as a RoCC coprocessor. The authors report SoftPosit-based verification for random inputs at es=2 and special cases at es=2 and es=3, application-level comparisons against IEEE-754 for image processing, transcendental series, FFT, and k-means, and FPGA synthesis results of 3507 slice LUTs, 1294 slice registers, and 100 MHz operation on an Artix-7-100T. The main claim is that this is the first complete posit-enabled RISC-V core with runtime es switching.

Significance. If the claims hold, PERI is a meaningful contribution: it provides a complete RV32F-compatible posit FPU, two integration paths into an open-source RISC-V core, and a hardware mechanism for switching between two exponent sizes. The paper's strengths include the explicit algorithms for posit decode/encode, FMA, division, square root, and conversions; the use of the SoftPosit reference library for arithmetic validation; and quantitative application results with confidence intervals. The synthesis numbers are also useful as a data point for posit FPU cost. However, the central 'first complete posit-enabled RISC-V core' claim rests on integration and dynamic-switching paths that are not validated by the experiments reported, and the application experiments depend on a manual software workaround that is presented with incorrect example encodings. With additional verification evidence and corrected software methodology, the paper would support its headline claim.

major comments (5)
  1. [§V-C, §IV-K, §V-B] The verification reported in Section V-C is narrower than the central claim. Random inputs were checked against SoftPosit only for es=2 operations, with special cases for es=2 and es=3; there is no reported random or directed testing of the dynamic-switching datapath described in Section IV-K (Equations 5–8), of the new FCVT.ES instruction (Table V), or of the RoCC accelerator integration path of Section V-B. Because the abstract's headline contribution is a complete core with runtime es switching, these untested paths are load-bearing. The authors should provide simulation logs, testbenches, or RTL artifacts that cover FCVT.ES, the es=2/3 switching logic, and execution through both integration modes.
  2. [§VI, §VII-A] The software porting workaround is not reproducible as presented. In the code snippet of Section VI, the bit patterns assigned to f1pt5 and f1pt2 are 0x44000000 and 0x4199999A; these correspond to approximately 512.0 and 12.2 in IEEE-754 single precision, not to 1.5 and 1.2. Since all application experiments in Section VII use this memcpy-based approach, the reported application results cannot be reproduced from the paper. The authors should correct the encodings and provide the exact posit bit patterns used for each application constant, along with the conversion scripts or tables used to generate them.
  3. [§IV-G, §VII-A] The motivation for adding round-to-zero (RTZ) rounding to the posit-to-integer conversion is presented post hoc from the JPEG compression result, but the mechanism is underspecified. Algorithm 7 line 15 checks 'if (rm = 1)' without defining how the RISC-V rm field maps to this bit, and Section IV-G does not specify which rm encodings select RTZ versus round-to-nearest. This is a correctness-relevant detail because the RTZ path is claimed to be the reason posit JPEG sizes match IEEE-754. Please specify the exact rm decoding and provide a directed test for the RTZ conversion path.
  4. [§VIII, Table XI] The synthesis methodology is not fully clear. Table XI says each module was synthesized separately, but the row totals and the 15% dynamic-switching overhead are presented as characteristics of the complete FPU. If the totals come from summing separately synthesized modules rather than a single integrated synthesis, the area and frequency numbers may not reflect the actual integrated design. Please clarify whether the 3507 LUT / 1294 register totals come from a full integrated posit FPU synthesis and state the post-integration timing closure method.
  5. [§VII] The application experiments lack enough methodological detail to assess the numerical comparisons. For the trigonometric, exponential, and FFT results, the paper does not specify the series truncation, range-reduction strategy, data types used for intermediate computations, or whether the same C code was compiled with the same compiler flags for the IEEE-754 and posit versions. These details matter because the claimed accuracy advantage could be affected by how the power series is evaluated. Please provide the source code, input data, and a description of the execution environment, including how the posit mode was selected on the SHAKTI core.
minor comments (7)
  1. [Algorithm 1, line 15] The notation 'k←(-ve)rc' is unclear; it should be written as 'k ← -rc' to match Equation 2.
  2. [§IV-K, Equations 5–8] The dynamic-switching modifications are presented as patch equations rather than integrated into Algorithms 1 and 2. It would be clearer to show the full modified decode/encode algorithms or state explicitly which lines are replaced by Equations 5–8.
  3. [§IV-G, Algorithm 7] The rounding-mode check 'if (rm = 1)' should be tied to the RISC-V instruction encoding, since the standard rm field is 3 bits; please specify the exact encoding used for round-to-zero versus round-to-nearest-even.
  4. [Tables VII and VIII] The confidence intervals are formatted ambiguously, e.g. '(1.20, 5.80) E-05'; this should read as '× 10^-5' or be converted to a consistent scientific notation.
  5. [Table VI] The caption says 'Original Posit (RNE)' but the first row appears to be the original image size; please clarify what 'Original' refers to in each column.
  6. [§V-C] The number of random tests and the set of operations tested are not reported. Please state how many random inputs were used per operation and list the operations included in the random and special-case suites.
  7. [§III-B] The RoCC instruction mapping is described at the format level, but the paper does not specify how the posit register file is addressed when xs1/xs2 are clear or how the xd bit controls writes back to the integer register file. A short example of a complete RoCC posit instruction would improve clarity.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: PERI's claims rest on external SoftPosit/synthesis validation, not on re-stating inputs.

full rationale

This paper is a hardware design and integration report, not a derivation from fitted parameters. Its central claims—first posit-enabled RISC-V core, feature-complete posit FPU, and dynamic es switching—are supported by implementation descriptions, algorithms, and measurements against external references. Random-input verification is checked against the SoftPosit library, an independent software implementation of the posit specification, and the paper states: 'Random inputs were generated and the corresponding outputs of each operation( es=2) were found to be in agreement with the result of the soft-posit library.' Application accuracy is measured against double-precision IEEE-754, which is an external ground truth for those experiments. FPGA area and timing are reported from Xilinx Vivado synthesis, an external tool, not from the paper's own assumptions. The only overlapping-author citation is the SHAKTI C-class core [17], used as the integration baseline; this is an existing open-source core and is not used to justify the correctness or novelty of the posit FPU. The dynamic-switching modifications in Equations (5)–(8) are design choices described within the paper, not fitted outcomes. The verification limitation noted in Section V-C—that random tests cover es=2 operations and only special cases for es=3, with no reported random tests for FCVT.ES or the RoCC accelerator path—is an evidentiary gap about implementation validation, not a circularity. No step in the paper reduces to its own inputs by construction, so the circularity score is 0.

Assumptions & free parameters 0 free parameters · 4 assumptions · 0 invented entities

None of the reported numbers is a fitted parameter; es=2 and es=3 are design choices, not constants obtained from the measured results. The FPU design introduces ISA artifacts such as the pcsr es-mode field and the FCVT.ES instruction, but no postulated physical entities.

assumptions (4)
  • domain assumption Posit format, rounding, and NaR semantics follow Gustafson and Yonemoto [8].
    All decoder and encoder algorithms in Section IV assume the standard posit definition from the cited paper.
  • domain assumption SoftPosit [25] is a correct reference implementation of posit arithmetic.
    Section V-C validates the FPU only by agreement with SoftPosit; if SoftPosit is wrong, the validation is void.
  • domain assumption The SHAKTI C-class core is RISC-V compliant and its BSV FPU interface can be swapped for the posit unit.
    Section V-A replaces the IEEE-754 FPU with the posit unit using the same BSV interface; this assumes interface and pipeline compatibility.
  • domain assumption Xilinx Vivado 2018.3 synthesis on the Artix-7 accurately reflects working hardware.
    The LUT, register, and 100 MHz claims in Section VIII come from synthesis, not from measured silicon or board bring-up.

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Cite this review

Pith. "Pith review of PERI: A Posit Enabled RISC-V Core." pith.science (2026). https://pith.science/paper/URL5D62W

@misc{pith2026190801466,
  author       = {Pith},
  title        = {Pith review of: PERI: A Posit Enabled RISC-V Core},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/URL5D62W}},
  note         = {Machine review of arXiv:1908.01466}
}
read the original abstract

Owing to the failure of Dennard's scaling the last decade has seen a steep growth of prominent new paradigms leveraging opportunities in computer architecture. Two technologies of interest are Posit and RISC-V. Posit was introduced in mid-2017 as a viable alternative to IEEE 754-2008. Posit promises more accuracy, higher dynamic range, and fewer unused states along with simpler hardware designs as compared to IEEE 754-2008. RISC-V, on the other hand, provides a commercial-grade open-source ISA. It is not only elegant and simple but also highly extensible and customizable, thereby facilitating novel micro-architectural research and exploration. In this paper, we bring these two technologies together and propose the first Posit Enabled RISC-V core. The paper provides insights on how the current 'F' extension and the custom op-code space of RISC-V can be leveraged/modified to support Posit arithmetic. We also present implementation details of a parameterized and feature-complete Posit FPU which is integrated with the RISC-V compliant SHAKTI C-class core either as an execution unit or as an accelerator. To fully leverage the potential of Posit, we further enhance our Posit FPU, with minimal overheads, to support two different exponent sizes (with posit-size being 32-bits). This allows applications to switch from high-accuracy computation mode to a mode with higher dynamic-range at run-time. In the absence of viable software tool-chain to enable porting of applications in the Posit domain, we present a workaround on how certain applications can be modified minimally to exploit the existing RISC-V tool-chain. We also provide examples of applications which can perform better with Posit as compared to IEEE 754-2008. The proposed Posit FPU consumes 3507 slice LUTs and 1294 slice registers on an Artix-7-100T Xilinx FPGA while capable of operating at 100 MHz.

Figures

Figures reproduced from arXiv: 1908.01466 by the authors.

Figure 1
Figure 1. Posit control and status register (pcsr). [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 2
Figure 2. Block diagram showing the different components of [PITH_FULL_IMAGE:figures/full_fig_p005_2.png] view at source ↗
Figure 3
Figure 3. Micro-architecture of the C-class core with [PITH_FULL_IMAGE:figures/full_fig_p009_3.png] view at source ↗
Figures from the paper (1 more)
Figure 4
Figure 4. Figure 4: Images used in image processing applications [PITH_FULL_IMAGE:figures/full_fig_p012_4.png]

Discussion (0). Continue with ORCID to comment.

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