ESBMC-LLB exposes function-block-hidden ladder logic bombs as safety violations, proves bomb-absence unboundedly, and synthesizes detonation triggers on public PLC benchmarks.
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2 Pith papers cite this work. Polarity classification is still indexing.
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Pith papers citing it
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2026 2representative citing papers
Hardware-faithful verification with a HAL descriptor eliminates all 54 false 16-bit overflow alarms on 123 real IEC 61131-3 programs while preserving robustness proofs.
citing papers explorer
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Detecting Ladder Logic Bombs in IEC 61131-3 PLC Programs using ESBMC-PLC+: A Formal Verification Approach with Trigger Synthesis
ESBMC-LLB exposes function-block-hidden ladder logic bombs as safety violations, proves bomb-absence unboundedly, and synthesizes detonation triggers on public PLC benchmarks.
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ESBMC-Arduino: Closing the Deployment Gap for Formal Verification of Open-Hardware PLCs
Hardware-faithful verification with a HAL descriptor eliminates all 54 false 16-bit overflow alarms on 123 real IEC 61131-3 programs while preserving robustness proofs.