A cycle-accurate Python model of the KID_READOUT FPGA chain identified spur sources and enabled firmware changes that cut LUT usage by 39%, flip-flops by 20%, and DSP slices by 29%, supporting over 800 MKIDs per feedline without performance loss.
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CONCERTO : Optimization of readout electronics
A cycle-accurate Python model of the KID_READOUT FPGA chain identified spur sources and enabled firmware changes that cut LUT usage by 39%, flip-flops by 20%, and DSP slices by 29%, supporting over 800 MKIDs per feedline without performance loss.