CONCERTO : Optimization of readout electronics

Christophe Hoarau (LPSC); Christophe Vescovi (LPSC); Mounir Abdkrimi (NEEL - MagSup); Olivier Bourrion (LPSC); Olivier Rossetto (LPSC)

arxiv: 2604.26438 · v1 · submitted 2026-04-29 · 📡 eess.SP

CONCERTO : Optimization of readout electronics

Mounir Abdkrimi (NEEL - MagSup) , Olivier Rossetto (LPSC) , Olivier Bourrion (LPSC) , Christophe Hoarau (LPSC) , Christophe Vescovi (LPSC) This is my paper

Pith reviewed 2026-05-07 10:51 UTC · model grok-4.3

classification 📡 eess.SP

keywords MKID readoutFPGA optimizationdigital twinmillimeter-wave instrumentsspur reductionresource usageCONCERTOdetector scaling

0 comments

The pith

A digital twin of the FPGA readout chain supports more than 800 MKIDs per feedline on the same hardware while preserving signal quality.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper develops a Python model that copies the FPGA digital signal processing chain bit by bit and cycle by cycle. This twin lets the team trace the sources of two spurs seen in CONCERTO data and redesign the firmware to cut logic, register, and DSP use by tens of percent. The changes fit twice as many detectors on each feedline without harming readout performance. A sympathetic reader would care because next-generation millimeter-wave cameras need far more detectors and this approach avoids the need for new or larger hardware platforms.

Core claim

By building a cycle- and bit-accurate Python digital twin of the full FPGA digital signal processing chain, the authors identified the origins of spurs in the existing CONCERTO readout and used the model to guide firmware optimizations that reduce LUT usage by 39 percentage points, flip-flops by 20.3 percentage points, and DSP slices by 28.98 percentage points. The resulting architecture supports more than 800 MKIDs per feedline on the same KID_READOUT hardware platform while preserving readout signal quality.

What carries the argument

The Python-based cycle- and bit-accurate digital twin of the full FPGA digital signal processing chain, which simulates internal signal behavior to guide firmware changes for lower resource use and reduced spurs.

If this is right

Spur amplitudes in the data decrease, raising the quality of science measurements from the instrument.
FPGA resource usage drops substantially while readout performance stays the same.
The same hardware platform now handles more than 800 MKIDs per feedline instead of 400.
Future high-resolution millimeter-wave instruments gain a scalable, resource-efficient readout solution.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

If the twin matches hardware behavior, similar models could speed up optimization for other FPGA-based MKID readouts facing scaling limits.
This simulation-first approach connects to the wider problem of increasing detector counts in cryogenic astronomy instruments without proportional hardware growth.
A direct test would be to use the twin to predict performance at 1000 MKIDs per feedline and then verify the prediction on hardware.

Load-bearing premise

The Python digital twin exactly reproduces the real FPGA timing, quantization, and analog-to-digital conversion behavior so that the spur reductions and resource savings seen in simulation will appear on the physical boards.

What would settle it

Loading the optimized firmware onto the actual KID_READOUT boards and measuring whether spur amplitudes drop and the reported resource savings hold when reading out more than 800 MKIDs per feedline.

read the original abstract

The CONCERTO millimeter-wave spectral-imaging instrument was deployed on the Atacama Pathfinder EXperiment (APEX), where it acquired science data between April 2021 and May 2023. The instrument features two focal-plane arrays, each composed of 2400 Microwave Kinetic Inductance Detectors (MKIDs). Each array is divided into six feedlines containing 400 MKIDs each, with each feedline read out by a dedicated FPGA-based board, KID_READOUT. The next-generation instrument aims to double the detector count per feedline, increasing it from 400 to 800 MKIDs. Achieving this requires a substantial scaling of the readout architecture and poses two key challenges for KID_READOUT: maintaining readout signal integrity and constraining firmware resource usage, as a direct upscaling of the existing design would exceed the available FPGA capacity. To overcome these limitations, we developed a Python-based, cycle-and bit-accurate digital twin of the full FPGA digital signal processing chain. This model enabled a detailed investigation of internal signal behavior and provided quantitative guidance for firmware optimization. Leveraging these insights, we identified the source of two spurs present in CONCERTO data and significantly reduced their amplitudes. At the same time, we achieved substantial reductions in firmware resource usage-39.0%pt in LUTs, 20.3%pt in flip-flops, and 28.98%pt in DSP slices-without degrading readout performance. The resulting architecture supports more than 800 MKIDs per feedline on the same hardware platform while preserving readout signal quality, offering a scalable and resource-efficient solution for future high-resolution millimeter-wave astronomical instruments.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

The CONCERTO team used a Python digital twin to diagnose spurs and cut FPGA resources enough to double MKIDs per feedline on the same board, but the scaling claim rests entirely on unverified simulation fidelity.

read the letter

The main point is that they modeled the full DSP chain in Python at cycle and bit accuracy, traced two spurs back to specific internal behaviors, and then reworked the firmware to drop LUT usage by 39 percentage points, flip-flops by 20, and DSP slices by 29 while claiming the readout quality stays the same. This lets the existing KID_READOUT hardware handle more than 800 MKIDs per feedline instead of 400. The work sits on top of their actual CONCERTO deployment on APEX, so the starting point is real instrument data rather than a blank slate. The resource numbers and the spur identification are concrete engineering outputs that could save time for other groups scaling MKID arrays on similar FPGAs. That part is useful and new for this specific board architecture. The modeling approach itself is not revolutionary, but the quantitative reductions they achieved are a legitimate incremental step. The soft spot is the missing link to hardware. All the reported improvements and the central scaling claim come from the twin alone. The abstract gives no before-and-after spectra, no error bars, and no description of loading the new firmware onto the physical boards and re-measuring spurs or noise. If the model misses any timing skew, quantization detail, or analog effect, the real performance could fall short of the simulated gains. That gap makes the “unchanged signal quality” statement harder to trust at face value. This paper is for instrument teams building or upgrading MKID readout electronics. FPGA engineers working on radio-astronomy or similar detector systems would get the most out of the resource trade-offs and the spur diagnosis method. It is not broad enough to shift the wider field, but the details are specific enough to be worth referee time. I would send it to peer review so the authors can add hardware validation if it exists or be asked for it if it does not.

Referee Report

2 major / 1 minor

Summary. The manuscript describes the use of a Python-based, cycle- and bit-accurate digital twin of the KID_READOUT FPGA DSP chain to optimize firmware for the CONCERTO instrument. The twin is used to identify the sources of two spurs observed in existing data and to redesign the architecture, yielding claimed resource reductions of 39.0 percentage points in LUTs, 20.3 in flip-flops, and 28.98 in DSP slices while asserting that readout signal quality is preserved, thereby enabling scaling from 400 to more than 800 MKIDs per feedline on the same hardware platform.

Significance. If the digital twin's fidelity to hardware is confirmed, the work offers a practical, model-guided approach to scaling MKID readout electronics without hardware changes, which is relevant for next-generation millimeter-wave instruments. The explicit resource savings and spur mitigation are concrete contributions, and the cycle-accurate modeling itself is a methodological strength that could be adopted more broadly.

major comments (2)

[Abstract] Abstract: The central claim that the optimized architecture 'supports more than 800 MKIDs per feedline ... while preserving readout signal quality' rests entirely on results from the Python digital twin, yet the manuscript provides no hardware-in-the-loop measurements, post-optimization FPGA tests, or direct comparisons of simulated versus measured spectra, timing, or quantization noise to establish that the twin reproduces real ADC, FPGA timing, and analog effects.
[Abstract] Abstract: Quantitative assertions of spur suppression and 'without degrading readout performance' are stated without accompanying before/after spectra, error bars on any metrics, or tabulated signal-quality figures of merit, so the magnitude and statistical significance of the claimed improvements cannot be assessed from the provided information.

minor comments (1)

[Abstract] The specific percentage-point resource savings are given in the abstract but are not cross-referenced to any table, figure, or section that shows the before-and-after utilization numbers or the exact design changes responsible for each reduction.

Simulated Author's Rebuttal

2 responses · 1 unresolved

We thank the referee for their careful review and constructive comments. We address the major comments point by point below, indicating where revisions have been made to the manuscript.

read point-by-point responses

Referee: [Abstract] Abstract: The central claim that the optimized architecture 'supports more than 800 MKIDs per feedline ... while preserving readout signal quality' rests entirely on results from the Python digital twin, yet the manuscript provides no hardware-in-the-loop measurements, post-optimization FPGA tests, or direct comparisons of simulated versus measured spectra, timing, or quantization noise to establish that the twin reproduces real ADC, FPGA timing, and analog effects.

Authors: The digital twin was validated through its ability to accurately reproduce the two spurs observed in the existing CONCERTO hardware data. Its cycle-accurate and bit-accurate design ensures faithful representation of the FPGA DSP chain for the current architecture. Resource savings are confirmed via FPGA synthesis reports. We acknowledge the absence of post-optimization hardware tests in the current work, as the redesign targets the next-generation instrument. The revised manuscript adds a dedicated section on twin validation against measured data and discusses expected fidelity for the optimized design. revision: yes
Referee: [Abstract] Abstract: Quantitative assertions of spur suppression and 'without degrading readout performance' are stated without accompanying before/after spectra, error bars on any metrics, or tabulated signal-quality figures of merit, so the magnitude and statistical significance of the claimed improvements cannot be assessed from the provided information.

Authors: We agree that additional quantitative detail strengthens the presentation. The revised manuscript now includes before-and-after spectra from the digital twin simulations demonstrating spur suppression, together with a table of signal-quality metrics including spur amplitudes, noise floor, and dynamic range. As these derive from deterministic bit-accurate simulations rather than repeated measurements, statistical error bars are not applicable; the reported changes are exact within the model. revision: yes

standing simulated objections not resolved

Post-optimization hardware-in-the-loop measurements and direct simulated-versus-measured comparisons for the new architecture, which have not yet been performed.

Circularity Check

0 steps flagged

No significant circularity in derivation chain

full rationale

The paper develops a Python cycle- and bit-accurate digital twin of the FPGA DSP chain, uses it to locate two spurs in existing CONCERTO data, and applies the resulting insights to redesign the firmware. Reported outcomes (spur amplitude reductions, LUT/FF/DSP savings of 39.0/20.3/28.98 percentage points, and the ability to support >800 MKIDs per feedline) are presented as direct consequences of those model-guided changes rather than being defined in terms of themselves. No equations, fitted parameters, self-citations, uniqueness theorems, or ansatzes appear in the provided text that would make any claimed prediction equivalent to its inputs by construction. The central scaling claim therefore rests on independent simulation results and does not reduce tautologically to the paper's starting assumptions.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

Work rests on standard digital-signal-processing assumptions for FPGA implementations and on the prior CONCERTO instrument characterization; no new free parameters or invented entities are introduced.

axioms (1)

domain assumption The Python model is cycle- and bit-accurate with respect to the target FPGA fabric.
Invoked to justify using simulation results as guidance for hardware changes.

pith-pipeline@v0.9.0 · 5627 in / 1152 out tokens · 40073 ms · 2026-05-07T10:51:28.110450+00:00 · methodology

discussion (0)

Reference graph

Works this paper leans on

13 extracted references · 13 canonical work pages

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O. Bourrion, C. Hoarau, J. Bounmy, D. Tourres, C. Vescovi, J.-L. Bouly et al.,Concerto: Readout and control electronics, Journal of Instrumentation17(2022) P10047

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J. Bounmy, C. Hoarau, J.-F. Macías-Pérez, A. Beelen, A. Benoît, O. Bourrion et al.,Concerto: Digital processing for finding and tuning lekids, Journal of Instrumentation17(2022) P08037

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Abdkrimi, O

M. Abdkrimi, O. Rossetto, O. Bourrion, C. Vescovi and C. Hoarau,A digital twin of the fpga digital signal processing chain for mkids readout: Root-cause analysis and mitigation of spurs,arXiv preprint arXiv:2603.04087(2026)

work page arXiv 2026
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Abdkrimi, O

M. Abdkrimi, O. Rossetto, O. Bourrion, C. Vescovi and C. Hoarau,Optimized fpga implementation of the cordic algorithm for a frequency multiplexed readout, in2025 14th Mediterranean Conference on Embedded Computing (MECO), IEEE, 2025

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D.-H. Ha and B.-J. Kim,Low-power quadrature demodulation using square-wave mixers in cmos rf receivers,IEEE Transactions on Circuits and Systems II: Express Briefs66(2019) 2042

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Alvarez, P

J. Alvarez, P. Garcia and A. Garcia,Fpga implementation of a digital lock-in amplifier based on square wave demodulation, in2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5, 2020

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S. Chattopadhyay and K. Mandal,Real-time spectral analysis using square-wave demodulation for software defined radios,Journal of Signal Processing Systems94(2022) 501

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1–4, IEEE, 2025

M.Abdkrimi, O.Rossetto, O.Bourrion, C.VescoviandC.Hoarau, Efficientfpgareadoutarchitecture for mkids: A dsp-light approach, in2025 20th International Conference on PhD Research in Microelectronics and Electronics (PRIME), pp. 1–4, IEEE, 2025

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Abdkrimi,Modeling of the readout chain and optimization of digital signal processing on FPGA for superconducting kinetic inductance detectors, Ph.D

M. Abdkrimi,Modeling of the readout chain and optimization of digital signal processing on FPGA for superconducting kinetic inductance detectors, Ph.D. thesis, Université Grenoble Alpes [2020-....], 2025. – 18 –

work page 2020
[13]

Abdkrimi, O

M. Abdkrimi, O. Rossetto, O. Bourrion, C. Vescovi and C. Hoarau,Modeling and analysis of digital-to-analog converter non-idealities in microwave kinetic inductance detectors readout, in2024 IEEE 28th Workshop on Signal and Power Integrity (SPI), pp. 1–4, IEEE, 2024. – 19 –

work page 2024

[1] [1]

P.K.Day, H.G.LeDuc, B.A.Mazin, A.VayonakisandJ.Zmuidzinas, Abroadbandsuperconducting detector suitable for large arrays,Nature425(2003) 817

work page 2003

[2] [2]

Klutsch,Modélisation des supraconducteurs et mesures, Ph.D

I. Klutsch,Modélisation des supraconducteurs et mesures, Ph.D. thesis, Institut National Polytechnique de Grenoble-INPG, 2003

work page 2003

[3] [3]

Ward-Thompson, P

D. Ward-Thompson, P. André, R. Crutcher and et al.,Protostars and planets v,University of Arizona Press(2007)

work page 2007

[4] [4]

Bourrion, C

O. Bourrion, C. Hoarau, J. Bounmy, D. Tourres, C. Vescovi, J.-L. Bouly et al.,Concerto: Readout and control electronics, Journal of Instrumentation17(2022) P10047

work page 2022

[5] [5]

Bounmy, C

J. Bounmy, C. Hoarau, J.-F. Macías-Pérez, A. Beelen, A. Benoît, O. Bourrion et al.,Concerto: Digital processing for finding and tuning lekids, Journal of Instrumentation17(2022) P08037

work page 2022

[6] [6]

Abdkrimi, O

M. Abdkrimi, O. Rossetto, O. Bourrion, C. Vescovi and C. Hoarau,A digital twin of the fpga digital signal processing chain for mkids readout: Root-cause analysis and mitigation of spurs,arXiv preprint arXiv:2603.04087(2026)

work page arXiv 2026

[7] [7]

Abdkrimi, O

M. Abdkrimi, O. Rossetto, O. Bourrion, C. Vescovi and C. Hoarau,Optimized fpga implementation of the cordic algorithm for a frequency multiplexed readout, in2025 14th Mediterranean Conference on Embedded Computing (MECO), IEEE, 2025

work page 2025

[8] [8]

Ha and B.-J

D.-H. Ha and B.-J. Kim,Low-power quadrature demodulation using square-wave mixers in cmos rf receivers,IEEE Transactions on Circuits and Systems II: Express Briefs66(2019) 2042

work page 2019

[9] [9]

Alvarez, P

J. Alvarez, P. Garcia and A. Garcia,Fpga implementation of a digital lock-in amplifier based on square wave demodulation, in2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5, 2020

work page 2020

[10] [10]

Chattopadhyay and K

S. Chattopadhyay and K. Mandal,Real-time spectral analysis using square-wave demodulation for software defined radios,Journal of Signal Processing Systems94(2022) 501

work page 2022

[11] [11]

1–4, IEEE, 2025

M.Abdkrimi, O.Rossetto, O.Bourrion, C.VescoviandC.Hoarau, Efficientfpgareadoutarchitecture for mkids: A dsp-light approach, in2025 20th International Conference on PhD Research in Microelectronics and Electronics (PRIME), pp. 1–4, IEEE, 2025

work page 2025

[12] [12]

Abdkrimi,Modeling of the readout chain and optimization of digital signal processing on FPGA for superconducting kinetic inductance detectors, Ph.D

M. Abdkrimi,Modeling of the readout chain and optimization of digital signal processing on FPGA for superconducting kinetic inductance detectors, Ph.D. thesis, Université Grenoble Alpes [2020-....], 2025. – 18 –

work page 2020

[13] [13]

Abdkrimi, O

M. Abdkrimi, O. Rossetto, O. Bourrion, C. Vescovi and C. Hoarau,Modeling and analysis of digital-to-analog converter non-idealities in microwave kinetic inductance detectors readout, in2024 IEEE 28th Workshop on Signal and Power Integrity (SPI), pp. 1–4, IEEE, 2024. – 19 –

work page 2024