A joint optimization framework for multi-die floorplanning and technology assignment that uses ML-based PPA estimation to optimize area, wirelength, performance, power, and cost, outperforming greedy baselines in 2.5D and 3D ICs.
Chiplet actuary: a quantitative cost model and multi-chiplet architecture exploration,
2 Pith papers cite this work. Polarity classification is still indexing.
2
Pith papers citing it
citation-role summary
background 1
citation-polarity summary
verdicts
UNVERDICTED 2roles
background 1polarities
background 1representative citing papers
A fairness-first Design Thinking method is proposed and tested in software architecture education to systematically address hidden fairness issues in digital systems.
citing papers explorer
-
Simultaneous Multi-die Floorplanning and Technology Assignment
A joint optimization framework for multi-die floorplanning and technology assignment that uses ML-based PPA estimation to optimize area, wirelength, performance, power, and cost, outperforming greedy baselines in 2.5D and 3D ICs.
-
Fairness-First Design Thinking for Software Architecture
A fairness-first Design Thinking method is proposed and tested in software architecture education to systematically address hidden fairness issues in digital systems.