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arxiv: 2502.10932 · v2 · submitted 2025-02-15 · 📡 eess.SY · cs.SY

Simultaneous Multi-die Floorplanning and Technology Assignment

Cristhian Roman-Vicharra , Prianka Sengupta , Runzhi Wang , Yiran Chen , Jiang Hu This is my paper

Pith reviewed 2026-05-23 03:10 UTC · model grok-4.3

classification 📡 eess.SY cs.SY
keywords multi-die floorplanningtechnology assignmentheterogeneous integration2.5D IC3D ICPPA estimationjoint optimizationmachine learning
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The pith

Treating technology assignment as a variable during multi-die floorplanning allows joint optimization of area, wirelength, performance, power, and cost.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper addresses heterogeneous integration where different dies can use different technologies, which couples the choice of technology to how the dies are physically arranged. Earlier floorplanning methods assumed a fixed technology and therefore could not explore trade-offs that arise when area, power, and speed change with technology. A machine-learning model supplies fast power-performance-area estimates so that technology choice and floorplan can be searched together. Experiments on 2.5D and 3D test cases, checked with a commercial tool, show the joint solutions beat a greedy sequential approach on all five metrics at once. The result matters because modern chip systems increasingly mix process nodes and the coupling between layout and technology had been left unaddressed.

Core claim

The central claim is that the first systematic multi-die floorplanning method that treats technology choice as an explicit decision variable, enabled by a machine-learning model for rapid PPA estimation under variable block areas, jointly optimizes area, wirelength, performance, power, and cost and produces solutions that significantly outperform a greedy baseline, with validation on commercial tools for both 2.5D and 3D ICs.

What carries the argument

The joint optimization procedure that incorporates machine-learning PPA estimates to accommodate block-area changes caused by technology assignment.

If this is right

  • Designers can obtain multi-objective improvements without first locking in a technology for each die.
  • The same framework applies to both 2.5D and 3D packaging flows.
  • Greedy sequential selection of technology then floorplan is shown to be suboptimal under realistic area variation.
  • Commercial-tool validation confirms the method produces layouts that are realizable in existing flows.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The approach could be extended to chiplet systems where each chiplet may target a different process node.
  • If the ML model remains accurate at larger scales, the method may shorten the design loop for heterogeneous stacks.
  • Similar joint formulations might apply to other coupled decisions such as partitioning and thermal management.

Load-bearing premise

The machine-learning model supplies PPA estimates accurate enough to guide the optimizer even when block areas vary with technology.

What would settle it

If layouts produced by the joint optimizer, when re-evaluated in the commercial tool, show no improvement over the greedy baseline on the reported metrics, the advantage claim would be falsified.

Figures

Figures reproduced from arXiv: 2502.10932 by Cristhian Roman-Vicharra, Jiang Hu, Prianka Sengupta, Runzhi Wang, Yiran Chen.

Figure 1
Figure 1. Figure 1: An overview of the proposed methodology. [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: (a) Architecture of fully-connected neural networks for the policy and [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Objective function f value for MMFP-SA/RL across iterations. D. Results on PPAC Optimization with 4 Silicon Dies Table III shows the results for the leon3-avnet design when the number of dies D is 4. The results show that MMFP-SA achieves average reductions of 7.2%, 6.5% and 3.2% in area, HPWL and cost, respectively, compared to the baseline. MMFP-RL further improves the reductions achieving 9.7%, 9% and 4… view at source ↗
Figure 5
Figure 5. Figure 5: Objective function f value for MMFP-SA/RL that performs inter-die refinement after every K moves/actions. H. Correlation Between Area, Cost and Power Although area is not explicitly included in our objective func￾tion (1). It can be controlled by varying the weights γ for cost and β for power, due to their correlation. This is confirmed by running MMFP-RL on the vga lcd design with various values of γ and … view at source ↗
Figure 6
Figure 6. Figure 6: Controlling area of vga lcd design in MMFP-RL via weighting factors for cost (γ) and power (β). VII. CONCLUSIONS This work provides the first study on multi-die and multi￾technology floorplanning, to the best of our knowledge. Post￾placement analysis using a commercial tool demonstrates that the pro￾posed techniques outperforms a na¨ıve baseline in terms of wirelength, area, power, timing and die cost. In … view at source ↗
read the original abstract

In heterogeneous integration, different dies may employ distinct technologies, making floorplanning across multiple dies inherently coupled with technology assignment. By assuming a fixed technology, almost all prior floorplanning studies were developed without addressing the challenge of technology assignment. This work presents the first systematic study of multi-die floorplanning that treats technology choice as a variable. To address the challenge of variable block areas, we incorporate a recent machine learning technique for rapid PPA estimation. Our methods jointly optimize area, wirelength, performance, power, and cost, thereby highlighting the importance of technology assignment. Experimental evaluations, validated with a commercial tool for both 2.5D and 3D ICs, demonstrate that our systematic optimizations significantly outperform a greedy approach.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The paper claims to present the first systematic study of multi-die floorplanning that treats technology assignment as a joint optimization variable rather than assuming fixed technologies. It incorporates a recent machine learning technique for rapid PPA estimation to handle technology-dependent block areas, enabling joint optimization of area, wirelength, performance, power, and cost. Experimental evaluations on 2.5D and 3D ICs, validated with a commercial tool, report that the approach significantly outperforms a greedy baseline.

Significance. If the central results hold under rigorous verification, the work would be significant for heterogeneous integration flows by establishing that technology assignment must be co-optimized with floorplanning rather than handled separately or greedily. The explicit use of commercial-tool validation and an external ML surrogate (rather than self-fitting) are positive features that support reproducibility and practical relevance.

major comments (2)
  1. [Experimental evaluations] The central claim that systematic joint optimization outperforms greedy relies on the ML PPA estimator remaining accurate when block areas vary with technology choice. The experimental evaluations section provides no quantitative error metrics, training coverage details for area-varying regimes, or side-by-side ML-versus-commercial-tool comparisons on the exact technology-assignment instances used in the optimization; without these, reported gains could be artifacts of surrogate bias.
  2. [Abstract and method description] The manuscript states that the ML technique is incorporated to address variable block areas, yet supplies no ablation or sensitivity analysis showing how estimation error propagates into the joint floorplan+technology solution quality. This is load-bearing because the abstract explicitly ties the outperformance claim to the ML-driven optimization.
minor comments (1)
  1. [Method] Notation for the multi-objective cost function and the interface between the ML estimator and the floorplanner should be defined more explicitly, ideally with a diagram or pseudocode.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive feedback. We address the major comments point-by-point below. The concerns identify gaps in the experimental validation of the ML PPA estimator; we agree these details should be added and will revise the manuscript accordingly.

read point-by-point responses

  1. Referee: [Experimental evaluations] The central claim that systematic joint optimization outperforms greedy relies on the ML PPA estimator remaining accurate when block areas vary with technology choice. The experimental evaluations section provides no quantitative error metrics, training coverage details for area-varying regimes, or side-by-side ML-versus-commercial-tool comparisons on the exact technology-assignment instances used in the optimization; without these, reported gains could be artifacts of surrogate bias.

    Authors: We agree that quantitative error metrics, training coverage details for area-varying regimes, and side-by-side ML-versus-commercial-tool comparisons on the exact instances are necessary to rule out surrogate bias. The manuscript reports commercial-tool validation but does not include these specific quantitative elements. In the revised version we will add the requested metrics, coverage details, and direct comparisons to substantiate that the reported gains are not artifacts of the surrogate. revision: yes

  2. Referee: [Abstract and method description] The manuscript states that the ML technique is incorporated to address variable block areas, yet supplies no ablation or sensitivity analysis showing how estimation error propagates into the joint floorplan+technology solution quality. This is load-bearing because the abstract explicitly ties the outperformance claim to the ML-driven optimization.

    Authors: We acknowledge that an ablation or sensitivity analysis demonstrating how estimation error propagates into solution quality is needed to support the abstract's claims. The current manuscript does not contain such an analysis. We will add a sensitivity study in the revision that quantifies the impact of ML error on the joint floorplan-plus-technology solutions. revision: yes

Circularity Check

0 steps flagged

No circularity: optimization uses external ML estimator and commercial-tool validation

full rationale

The paper's core method jointly optimizes floorplanning and technology assignment by incorporating a recent (external) ML technique for PPA estimation to handle variable block areas, then validates final results against a commercial tool on 2.5D/3D IC instances. No derivation step reduces by construction to its own fitted inputs, self-citations, or renamings; the performance claims rest on the external validator rather than internal consistency alone. This matches the expected non-circular case for a paper whose central results are externally falsifiable.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

Abstract-only view yields limited visibility into parameters or assumptions; the central modeling choice is reliance on an external ML PPA estimator whose accuracy is not quantified here.

axioms (1)
  • domain assumption Machine learning technique supplies sufficiently accurate and rapid PPA estimates when block areas change with technology
    Invoked to handle variable block areas arising from technology assignment (abstract).

pith-pipeline@v0.9.0 · 5656 in / 1225 out tokens · 29443 ms · 2026-05-23T03:10:31.511543+00:00 · methodology

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Reference graph

Works this paper leans on

23 extracted references · 23 canonical work pages · 2 internal anchors

  1. [1]

    Multiple chip planning for chip- interposer codesign,

    Y .-K. Ho and Y .-W. Chang, “Multiple chip planning for chip- interposer codesign,” in Proceedings of the 50th Annual Design Automation Conference , ser. DAC ’13. New York, NY , USA: Association for Computing Machinery, 2013. [Online]. Available: https://doi.org/10.1145/2463209.2488767

    work page doi:10.1145/2463209.2488767 2013

  2. [2]

    Floorplanning for embedded multi-die interconnect bridge packages,

    C.-C. Lee and Y .-W. Chang, “Floorplanning for embedded multi-die interconnect bridge packages,” in 2023 IEEE/ACM International Con- ference on Computer Aided Design (ICCAD) , 2023, pp. 1–8

    work page 2023

  3. [3]

    Optimal die placement for interposer-based 3d ics,

    S. Osmolovskyi, J. Knechtel, I. L. Markov, and J. Lienig, “Optimal die placement for interposer-based 3d ics,” in 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), 2018, pp. 513–520

    work page 2018

  4. [4]

    Tap-2.5d: A thermally-aware chiplet placement methodology for 2.5d systems,

    Y . Ma, L. Delshadtehrani, C. Demirkiran, J. L. Abellan, and A. Joshi, “Tap-2.5d: A thermally-aware chiplet placement methodology for 2.5d systems,” in 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021, pp. 1246–1251

    work page 2021

  5. [5]

    Transitive closure graph-based warpage-aware floorplanning for package designs,

    Y . Hsu, M.-H. Chung, Y .-W. Chang, and C.-H. Lin, “Transitive closure graph-based warpage-aware floorplanning for package designs,” in Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design , ser. ICCAD ’22. New York, NY , USA: Association for Computing Machinery, 2022. [Online]. Available: https://doi.org/10.1145/3508352.3549354

    work page doi:10.1145/3508352.3549354 2022

  6. [6]

    Rlplanner: Reinforcement learning based floorplanning for chiplets with fast thermal analysis,

    Y . Duan, X. Liu, Z. Yu, H. Wu, L. Shao, and X. Zhu, “Rlplanner: Reinforcement learning based floorplanning for chiplets with fast thermal analysis,” in 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2024, pp. 1–2

    work page 2024

  7. [7]

    Large reasoning models for 3d floorplanning in eda: Learning from imperfections,

    F. Amin, N. Rouf, T.-H. Pan, M. K. I. Shafi, and P. D. Franzon, “Large reasoning models for 3d floorplanning in eda: Learning from imperfections,” 2024. [Online]. Available: https: //arxiv.org/abs/2406.10538

    work page arXiv 2024

  8. [8]

    Floorplet: Performance-aware floorplan framework for chiplet integration,

    S. Chen, S. Li, Z. Zhuang, S. Zheng, Z. Liang, T.-Y . Ho, B. Yu, and A. L. Sangiovanni-Vincentelli, “Floorplet: Performance-aware floorplan framework for chiplet integration,” IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems , vol. 43, no. 6, pp. 1638–1649, 2024

    work page 2024

  9. [9]

    Physical design challenges in modern heterogeneous integration,

    Y .-W. Chang, “Physical design challenges in modern heterogeneous integration,” in Proceedings of the 2024 International Symposium on Physical Design , ser. ISPD ’24. New York, NY , USA: Association for Computing Machinery, 2024, p. 125–134. [Online]. Available: https://doi.org/10.1145/3626184.3639690

    work page doi:10.1145/3626184.3639690 2024

  10. [10]

    How good is your verilog rtl code? a quick answer from machine learning,

    P. Sengupta, A. Tyagi, Y . Chen, and J. Hu, “How good is your verilog rtl code? a quick answer from machine learning,” in Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design , ser. ICCAD ’22. New York, NY , USA: Association for Computing Machinery, 2022. [Online]. Available: https://doi.org/10.1145/3508352.3549375

    work page doi:10.1145/3508352.3549375 2022

  11. [11]

    Goodfloorplan: Graph convolutional network and reinforce- ment learning-based floorplanning,

    Q. Xu, H. Geng, S. Chen, B. Yuan, C. Zhuo, Y . Kang, and X. Wen, “Goodfloorplan: Graph convolutional network and reinforce- ment learning-based floorplanning,” IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems , vol. 41, no. 10, pp. 3492–3502, 2022

    work page 2022

  12. [12]

    Chiplet actuary: a quantitative cost model and multi-chiplet architecture exploration,

    Y . Feng and K. Ma, “Chiplet actuary: a quantitative cost model and multi-chiplet architecture exploration,” in Proceedings of the 59th ACM/IEEE Design Automation Conference , ser. DAC ’22. New York, NY , USA: Association for Computing Machinery, 2022, p. 121–126. [Online]. Available: https://doi.org/10.1145/3489517.3530428

    work page doi:10.1145/3489517.3530428 2022

  13. [13]

    The use and evaluation of yield models in integrated circuit manufacturing,

    J. Cunningham, “The use and evaluation of yield models in integrated circuit manufacturing,” IEEE Transactions on Semiconductor Manufac- turing, vol. 3, no. 2, pp. 60–71, 1990

    work page 1990

  14. [14]

    Multi-package co- design for chiplet integration,

    Z. Zhuang, B. Yu, K.-Y . Chao, and T.-Y . Ho, “Multi-package co- design for chiplet integration,” in Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design , ser. ICCAD ’22. New York, NY , USA: Association for Computing Machinery, 2022. [Online]. Available: https://doi.org/10.1145/3508352.3549404

    work page doi:10.1145/3508352.3549404 2022

  15. [15]

    Proximal Policy Optimization Algorithms

    J. Schulman, F. Wolski, P. Dhariwal, A. Radford, and O. Klimov, “Proximal policy optimization algorithms,” 2017. [Online]. Available: https://arxiv.org/abs/1707.06347

    work page internal anchor Pith review Pith/arXiv arXiv 2017

  16. [16]

    B*-trees: a new representation for non-slicing floorplans,

    Y .-C. Chang, Y .-W. Chang, G.-M. Wu, and S.-W. Wu, “B*-trees: a new representation for non-slicing floorplans,” in Proceedings of the 37th Annual Design Automation Conference , ser. DAC ’00. New York, NY , USA: Association for Computing Machinery, 2000, p. 458–463. [Online]. Available: https://doi.org/10.1145/337292.337541

    work page doi:10.1145/337292.337541 2000

  17. [17]

    IWLS 2005 benchmarks,

    C. Albrecht, “IWLS 2005 benchmarks,” in International Workshop for Logic Synthesis (IWLS) , vol. 9, 2005

    work page 2005

  18. [18]

    Openpiton: An open source manycore research framework,

    J. Balkind, M. McKeown, Y . Fu, T. Nguyen, Y . Zhou, A. Lavrov, M. Shahrad, A. Fuchs, S. Payne, X. Liang, M. Matl, and D. Wentzlaff, “Openpiton: An open source manycore research framework,” inProceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems, ser. ASPLOS ’16. New York, NY , US...

    work page doi:10.1145/2872362.2872414 2016

  19. [19]

    Freepdk: An open-source variation-aware design kit,

    J. E. Stine, I. Castellanos, M. Wood, J. Henson, F. Love, W. R. Davis, P. D. Franzon, M. Bucher, S. Basavarajaiah, J. Oh, and R. Jenkal, “Freepdk: An open-source variation-aware design kit,” in 2007 IEEE In- ternational Conference on Microelectronic Systems Education (MSE’07), 2007, pp. 173–174

    work page 2007

  20. [20]

    Asap7 predictive design kit development and cell design technology co-optimization: Invited paper,

    V . Vashishtha, M. Vangala, and L. T. Clark, “Asap7 predictive design kit development and cell design technology co-optimization: Invited paper,” in 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2017, pp. 992–998

    work page 2017

  21. [21]

    Multilevel hypergraph partitioning: application in vlsi domain,

    G. Karypis, R. Aggarwal, V . Kumar, and S. Shekhar, “Multilevel hypergraph partitioning: application in vlsi domain,” in Proceedings of the 34th Annual Design Automation Conference , ser. DAC ’97. New York, NY , USA: Association for Computing Machinery, 1997, p. 526–529. [Online]. Available: https://doi.org/10.1145/266021.266273

    work page doi:10.1145/266021.266273 1997

  22. [22]

    Spinning Up in Deep Reinforcement Learning,

    J. Achiam, “Spinning Up in Deep Reinforcement Learning,” 2018

    work page 2018

  23. [23]

    Gymnasium: A Standard Interface for Reinforcement Learning Environments

    M. Towers, A. Kwiatkowski, J. Terry, J. U. Balis, G. De Cola, T. Deleu, M. Goul ˜ao, A. Kallinteris, M. Krimmel, A. KG et al. , “Gymnasium: A standard interface for reinforcement learning environments,” arXiv preprint arXiv:2407.17032, 2024

    work page internal anchor Pith review Pith/arXiv arXiv 2024